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Schematic Diagrams
POWER ON SEQUENCE
Sheet 55 of 55
POWER ON
SEQUENCE
B - 56 POWER ON SEQUENCE
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W370ET/ W350ET POWER SEQUENCE
VCCRTC
RTCRST#
37.5ms
DD_ON#
2ms
3V
5V
3.2ms
PWRBTN#
RSMRST#
ACPRESENT
SLP_S4# (SUSC)
1.5V
SLP_S3# (SUSB)
SUS_PWR_DN_ACK
3.3VS
5VS
1.5VS
VTT_MEM(0.75V)
1.5VS _CPU
1.8VS(VccPLL)
1.05VS
1.05VS_VTT
0.85VS
H_VTTPWRGD(ALL_SYS_PWRGD)
IMVP_VR_EN
VCORE
VGFX_CORE
DELAY_PWRGD
PM_PCH_PWROK (APWROK)
SYS_PWROK
DRAMPWROK
H_CPUPWGD
S4_STATE#
PLT_RST#
IMVP_VR_EN
CPU SVID BUS
VCORE
MVP_PWRGD (VR_Ready)
56ms
229ms
1.6mS
20us
1.6mS
2mS
1.95mS
2.7mS
1.7mS
4.38mS
1.25ms
7mS
8mS
11mS
11mS
13.7mS
13.7mS
14.2mS
136mS
136mS
217mS
239mS
241mS
241mS
setVID
A
SLOW
C
SPEC MIN MAX5ms
packet
K
SPEC MAX500us
SPEC MIN50us~MAX2000us
SPEC MAX50us
SPEC MAX5ms
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