Startup Timing - Texas Instruments 2 Series Manual

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There are some restrictions to how the cells are connected during manufacturing:
The cells in a stack cannot be randomly connected to any VC pin on the device, such as the lowest
cell (cell-1) connected to VC5, while the top cell (cell-5) is connected to VC2, and so on. It is important
to connect the cells in the stack in ascending pin order, with the lowest cell (cell-1) connected between
VC1 and VC0, the next higher voltage cell (cell-2) connected between VC2 and VC1, and so on.
• The random cell connection support is possible due to high voltage tolerance on pins VC1–VC5.
VC0 has a lower voltage tolerance. This is because VC0 should be connected through the series
cell input resistor to the VSS pin on the PCB, before any cells are attached to the PCB. Thus, the
VC0 pin voltage is expected to remain close to the VSS pin voltage during cell attach. If VC0 is
not connected through the series resistor to VSS on the PCB, then cells cannot be connected in
random sequence.
• Each of the VC1–VC5 pins includes a diode between the pin and the adjacent lower cell input pin (that is,
between VC5 and VC4A, between VC4B and VC3A, and so on), which is reverse biased in normal operation.
This means an upper cell input pin should not be driven to a low voltage while a lower cell input pin is driven
to a higher voltage, since this would forward bias these diodes. During cell attach, the cell input terminals
should generally be floating before they are connected to the appropriate cell. It is expected that transient
current will flow briefly when each cell is attached, but the cell voltages will quickly stabilize to a state without
DC current flowing through the diodes. However, if a large capacitance is included between a cell input pin
and another terminal (such as VSS or another cell input pin), the transient current may become excessive
and lead to device heating. Therefore, it is recommended to limit capacitances applied at each cell input pin
to the values recommended in the specifications.

8.2.5 Startup Timing

At initial power-up of the BQ76905 device from a SHUTDOWN state, the device progresses through a
sequence of events before entering NORMAL mode operation. These are described in
configuration, with approximate timing shown.
STEP
Wakeup event
REGOUT powered
First Cell-1 measurement completed
INITCOMP, ADSCAN, and FULLSCAN
asserted (5 series)
FETs enabled (5 series)
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Note
Note
Table 8-2. Startup Sequence and Timing
COMMENT
Either the TS pin or the VC0 pin is pulled
up, triggering the device to exit SHUTDOWN
mode
Measured with the OTP programmed to
autonomously power the REGOUT LDO
Data from first measurement of Cell-1 can be
read back
Measured with the OTP programmed
to provide the INITCOMP and
ADSCAN bits in the Alarm signal
on the ALERT pin [CVADCSPEED1:0]
= 0x0, [IADCSPEED1:0] = 0x0,
[SSADCSPEED1:0] = 0x0
Measured with the OTP
programmed to autonomously
enable FETs. [CVADCSPEED1:0]
= 0x0, [IADCSPEED1:0] = 0x0,
[SSADCSPEED1:0] = 0x0
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APPROXIMATE TIME (RELATIVE TO
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BQ76905
BQ76905
SLUSE97 – NOVEMBER 2023
Table 8-2 for an example
WAKEUP EVENT)
0
2.6 ms
3.2 ms
8.6 ms
8.6 ms
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