Operating From 3.3 V Standby; Standby Mode; Xnor Tree Test Mode; Power-On Default - Analog Devices dBCool ADT7475 Manual

PWM Configuration Register (Reg. 0x5C to Reg. 0x5E)
<7:5> BHVR
111 = manual mode.
Once under manual control, each PWM output can be manu-
ally updated by writing to Reg. 0x30 to Reg. 0x32 (PWMx
current duty cycle registers).
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers, which
allow the PWM duty cycle for each output to be set anywhere
from 0% to 100% in steps of 0.39%.
The value to be programmed into the PWM
given by
Value (decimal) = PWM
Example 1: For a PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128 (decimal)
Value = 128 (decimal) or 0x80 (hex)
Example 2: For a PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85 (decimal)
Value = 85 (decimal) or 0x54 (hex)
PWM Duty Cycle Registers
Reg. 0x30 PWM1 Duty Cycle = 0x00 (0% default)
Reg. 0x31 PWM2 Duty Cycle = 0x00 (0% default)
Reg. 0x32 PWM3 Duty Cycle = 0x00 (0% default)
By reading the PWMx current duty cycle registers, the user can
keep track of the current duty cycle on each PWM output, even
when the fans are running in automatic fan speed control mode
or acoustic enhancement mode. See the Programming the
Automatic Fan Speed Control Loop section for details.

OPERATING FROM 3.3 V STANDBY

The ADT7475 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5 states,
the core voltage of the processor is lowered in these states.
When monitoring THERM , the THERM timer should be
disabled during these states.

STANDBY MODE

The ADT7475 has been specifically designed to respond to the
STBY supply. In computers that support S3 and S5 states, the
core voltage of the processor is lowered in these states. When
monitoring THERM , the THERM timer should be disabled
during these states.
register is
MIN
/0.39
MIN
When the V
CCP
following occurs:
1. Status Bit 1 (V
2. SMBALERT is generated, if enabled.
3. THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
Once the core voltage, V
everything is re-enabled and the system resumes normal
operation.

XNOR TREE TEST MODE

The ADT7475 includes an XNOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying stimulus to the pins included in the XNOR tree, it is
possible to detect opens or shorts on the system board.
Figure 41 shows the signals that are exercised in the XNOR
tree test mode. The XNOR tree test is invoked by setting Bit 0
(XEN) of the XNOR tree test enable register (Reg. 0x6F).

POWER-ON DEFAULT

When the ADT7475 is powered up, monitoring is off by default
and the PWM outputs go to 100%. All necessary registers then
need to be configured via the SMBus for the appropriate
functions to operate.
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voltage drops below the V
CCP
) in Status Register 1 is set.
CCP
, goes above the V
CCP
TACH1
TACH2
TACH3
TACH4
PWM2
PWM3 PWM1/XTO
Figure 41. XNOR Tree Test
ADT7475
low limit, the
low limit,
CCP