Status Registers - Analog Devices dBCool ADT7475 Manual

As mentioned previously, the ADC performs round-robin
conversions. The total monitoring cycle time for averaged
voltage and temperature monitoring is 146 ms. The total
monitoring cycle time for voltage and temperature moni-
toring with averaging disabled is 19 ms. The ADT7475 is a
derivative of the ADT7467. As a result, the total conversion
time in the ADT7475 is the same as the total conversion time
of the ADT7467.
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.

STATUS REGISTERS

The results of limit comparisons are stored in Status Register 1
and Status Register 2. The status register bit for each channel
reflects the status of the last measurement and limit comparison
on that channel. If a measurement is within limits, the corre-
sponding status register bit is cleared to 0. If the measurement
is out-of-limits, the corresponding status register bit is set to 1.
The state of the various measurement channels can be polled by
reading the status registers over the serial bus. In Bit 7 (OOL) of
Status Register 1 (Reg. 0x41), 1 means that an out-of-limit event
has been flagged in Status Register 2. This means that the user
needs only to read Status Register 2 when this bit is set. Alterna-
tively, Pin 5 or Pin 9 can be configured as an SMBALERT output.
This automatically notifies the system supervisor of an out-of-
limit condition. Reading the status registers clears the appropriate
status bit as long as the error condition that caused the interrupt
has cleared.
Status register bits are sticky. Whenever a status bit is set,
indicating an out-of-limit condition, it remains set even if the
event that caused it has gone away (until read). The only way to
clear the status bit is to read the status register after the event
has gone away. Interrupt status mask registers (Reg. 0x74, 0x75)
allow individual interrupt sources to be masked from causing
an SMBALERT . However, if one of these masked interrupt
sources goes out-of-limit, its associated status bit is set in the
interrupt status registers.
Status Register 1 (Reg. 0x41)
Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and
Status Register 2 should be read.
Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has
been exceeded.
Bit 5 (LT) = 1, local temperature high or low limit has been
exceeded.
Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has
been exceeded.
) = 1, V high or low limit has been exceeded.
Bit 2 (V
CC CC
Bit 1 (V ) = 1, V high or low limit has been exceeded.
CCP CCP
Status Register 2 (Reg. 0x42)
Bit 7 (D2) = 1, indicates an open or short on D2+/D2– inputs.
Bit 6 (D1) = 1, indicates an open or short on D1+/D1– inputs.
Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum
speed. Alternatively, indicates the THERM limit has been
exceeded, if the THERM function is used.
Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below minimum
speed.
Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below minimum
speed.
Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below minimum
speed.
Bit 1 (OVT) = 1, indicates a THERM overtemperature limit has
been exceeded.
SMBALERT Interrupt Behavior
The ADT7475 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. Note
how the SMBALERT output and status bits behave when
writing interrupt handler software.
HIGH LIMIT
TEMPERATURE
"STICKY"
STATUS BIT
SMBALERT
Figure 25. SMBALERT and Status Bit Behavior
Figure 25 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides and the status register is read. The status bits are referred
to as sticky, because they remain set until read by software. This
ensures an out-of-limit event cannot be missed, if software is
polling the device periodically. Note the SMBALERT output
remains low for the entire duration that a reading is out-of-limit
and until the status register has been read. This has implications
on how software handles the interrupt.
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CLEARED ON READ
(TEMP BELOW LIMIT)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
ADT7475