Dram; Smartmedia Card; Serial Eeprom; Vga Lcd/Crt Interface - GE Marquette MAC 5000 Field Service Manual

CPU Theory of Operation: Theory of Operation

SmartMedia Card

Serial EEPROM

VGA LCD/CRT Interface

Acquisition Module
Transceiver/Power
Thermal Printhead
Power/Pixel Test Logic
5-12

DRAM

Program code and working data is stored in a single 1MWord bank of
32-bit wide memory (4MBytes). EDO DRAM is used to achieve moderate
burst rates (75MBytes/sec @ 26MHz bus speed). All bus timing and
refresh control is performed by the FPGA.
FPGA configuration data and system software are stored on a
SmartMedia card. The system can accommodate sizes from 2MBytes to
16MBytes. To reduce loading on the processor address/data busses, the
SmartMedia card is accessed by the StrongARM via the isolated XBus.
Special gating is provided for the SmartMedia CS pin to reduce
susceptibility to accidental writes.
System setup information, option enables and other machine specific
data is stored in a 16KByte serial EEPROM. The interface to the EEPROM
is provided by the FPGA.
Control for a standard VGA format (640 x 480 pixels) LC display is
provided by the FPGA. A connector is provided for an external CCFL
backlight inverter as well as two digital controls for On/Off and
brightness.
MAC 5000 acquires ECG data with a new generation CAM-14 acquisition
module. The FPGA provides the interface logic. Clocks and commands
are transmitted to the acquisition module on a balanced RS485 line.
Data is received similarly. Both directions are handled by a single RS485
Switch
transceiver. Power to the acquisition module is provided by a software
controlled switch/current limiter.
Normal system operation is sufficient to verify the correct operation of
the acquisition module interface. The module power switch/current
limiter may be tested against spec as indicated elsewhere in this
document.
The FPGA provides all the interface logic for the thermal print head.
Power is controlled by a MOSFET switch whose gate drive is provided by
a charge pump voltage doubler driven by the FPGA.
Additional circuitry is supplied to allow the measurement of individual
dot resistance for automatic strobe width compensation and blown dot
detection. A switchable constant current source (6mA) applies a test
current to the TPH power bus. The TPH power bus voltage is then
measured by Larry (one of the four analog inputs he continuously
monitors). By loading a single black dot into the print head, it is possible
to measure its resistance. A typical TPH has an average dot resistance of
MAC 5000 resting ECG analysis system
2000657-002
Revision B