Pine Technology PT-730A User Manual page 28

Pentium pci main board
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DRAM RAS# Precharge Time
This option specifies the number of CPU clocks used for memory RAS# signal percharge time.
DRAM RAS# low to CAS# low
This option specifies the delay (CPU clocks) for memory RAS# asserted to memory CAS# asserted.
DRAM Page Mode Option
This option enables or disables Page Mode function of the DRAM.
L2 Cache Update Scheme
This option specifies the L2 cache update scheme as Write Through or Write Back
Tag Option
This option programs the 8-bit tag SRAM to contain 7-bit or 8-bit tag.
Cache Read Wait States
This option specifies the number of wait states when CPU reads cache memory.
Cache Write Wait States
This option specifies the number of wait states when CPU writes cache memory.
Cache Tag Hit Wait States
This option specifies the number of wait states when there is a tag hit.
Video BIOS Cacheable
Enable this option will copy video display card BIOS to cache to improve performance.
Keyboard Controller Clock
This option specifies keyboard controller clock speed as a fraction of PCI clock speed.
ISA Bus Clock Option
This option specifies ISA clock speed as a fraction of PCI clock speed.
Keyboard Emulation
Enable this option will emulate Keyboard's Gate A20 Function and keyboard's fast Reset.
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