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Connector Configuration
The Legend-V mainboard supports up to three 168 pin 3.3V un-buffered
DIMM, provides a flexible size from 8MB up to 384MB SDRAM memory or
from 8MB up to 768MB EDO memory. The following set of rules allows for
optimum configurations.
Rules for populating a 440LX 0memory array:
DIMM sockets can be populated in any order. However, to take
advantage of potentially faster MA timing it is recommended to populate
sockets in order.
The DRAM Timing register, which provides the DRAM speed grade
control for the entire memory array, must be programmed to use the
timings of the slowest DRAMs installed.
Possible EDO DIMM memory size is 8MB, 16MB , 32MB, 64MB,
128MB, 256MB in each DIMM socket.
Possible SDRAM memory size is 8MB, 16MB , 32MB, 64MB, 128MB
in each DIMM socket.
Clear CMOS
Note: You must power down the AC supply(110/220V) when you want to
clear CMOS.
2 - 6
Clear CMOS :
Normal :
Close Once
1 2
3
JP6
1 2
3
JP6
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