Clevo W550SU1 Service Manual page 60

Schematic Diagrams
Processor 2/7- CLK, MISC
Processor Pullups/Pull downs
VCCIO_OUT
D
Sheet 3 of 45
Processor 2/7 -
C
CLK, MISC
VCCIO_OUT
B
SSC CLOCK TERMINATION
STUFF R4R15 & R4R12
ONLY WHEN SSC CLOCK
NOT USED
Buffered reset to CPU
A
B - 4 Processor 2/7- CLK, MISC
5 4
Haswell Processor 2/7 ( CLK,MISC,JTAG )
62_04 R309 H_PROCHOT#
10K_04 R297 H_CPUPWRGD_R
TRACE WIDTH 10MIL, LENGTH <500MILS
SKTOCC#
H_CATERR#
H_PECI_ISO
R315 *20mil_04
18,30 H_PECI
VCCST
R310 56_1%_04 H_PROCHOT#_D
35 H_PROCHOT#
H_THRMTRIP_R_N
18 H_THRMTRIP_R_N
16 H_PM_SYNC
H_CPUPWRGD R298 *20mil_04 H_CPUPWRGD_R
18 H_CPUPWRGD
PMSYS_PWRGD_BUF R70 0_04 VDDPWRGOOD_R
BUF_CPU_RST# CPU_RST_N_R
R314 *0_04
R313 *20mil_04
18 CPU_RST_N
22 PCH_CK_DP_N
22 PCH_CK_DP_P
22 PCH_SSC_N
22 PCH_SSC_P
22 CLK_EXP_N
22 CLK_EXP_P
R47
*10K_04
1.05V_LAN_M VCCST
PCH_SSC_P
PCH_SSC_N
R37 *0_04
R45
*10K_04
C50
*22u_6.3V_X5R_08
R321 *2K_1%_04 BUF_CPU_RST#
17 PLT_RST#
R319
*1K_1%_04
5 4
3
U17B Haswell rPGA EDS
AP32 MISC AP3 SM_RCOMP_0
SKTOCC SM_RCOMP_0
AR3 SM_RCOMP_1
SM_RCOMP_1
AN32 AP2 SM_RCOMP_2
CATERR SM_RCOMP_2
AR27 AN3 CPUDRAMRST#
PECI SM_DRAMRST
AK31
FC
AM30 AR29 XDP_PRDY#
PROCHOT PRDY
AM35 AT29 XDP_PREQ#
THERMTRIP PREQ
AM34 XDP_TCLK
TCK
AN33 XDP_TMS
TMS
AM33 XDP_TRST#
TRST
AT28 AM31 XDP_TDI_R
PM_SYNC TDI
AL34 AL33 XDP_TDO_R
PWRGOOD TDO
AC10 AP33 XDP_DBR_R
SM_DRAMPWROK DBR
AT26
PLTRSTIN
AR30 XDP_BPM0
BPM_N_0
AN31 XDP_BPM1
BPM_N_1
G28 AN29 XDP_BPM2
DPLL_REF_CLKN BPM_N_2
H28 AP31 XDP_BPM3
DPLL_REF_CLKP BPM_N_3
PCH_SSC_N XDP_BPM4
F27 AP30
SSC_DPLL_REF_CLKN BPM_N_4
PCH_SSC_P E27 AN28 XDP_BPM5
SSC_DPLL_REF_CLKP BPM_N_5
D26 AP29 XDP_BPM6
BCLKN BPM_N_6
E26 AP28 XDP_BPM7
BCLKP BPM_N_7
2 OF 9
H_PROCHOT#
Q14
G C338
30 H_PROCHOT_EC
2SK3018S3
R317 47p_50V_NPO_04
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
S3 circuit:- DRAM_RST# to memory
should be high during S3
V_VDDQ_DIMM
R326
1K_04
R323 *0_04
Q15
2SK3018S3
CPUDRAMRST# S D R325 1K_04
DDR3_DRAMRST#
DRAMRST_CNTRL 10,15,9
R322 C340
4.99K_1%_04 0.047u_10V_X7R_04
10,34,5,9 V_VDDQ_DIMM
5,6 VCCIO_OUT
20,21,32,35,5 1.05V_LAN_M
12,19,2,21,23,24,26,27,31,32,34
10,11,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,35,6,9
3
2 1
H_THRMTRIP_R_N *100_04
CPU_RST_N *75_04
DDR3 Compensation Signals
SM_RCOMP_0 R327
SM_RCOMP_1 R324
SM_RCOMP_2 R328
PU/PD for JTAG signals
1.05V_LAN_M
R44 *51_04
R40 *51_04
R38 *51_04
1.05V_LAN_M
R302 *51_04
R303 51_04
R300
*51_04
3.3VS
XDP_TDO_R
R307 *1K_04
R299
If PROCHOT# is not used,
*100_04
then it must be terminated
with a 56- +-5% pull-up
resistor to 1.05VS_VTT .
S3 circuit:- DRAM PWR GOOD lCIRCUIT
V_VDDQ_DIMM
R77
10K_04
R76 *20mil_04
16 PM_DRAM_PWRGD
10,9
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
Title Title Title
[03] Haswell 2/7-CLK/MISC [03] Haswell 2/7-CLK/MISC [03] Haswell 2/7-CLK/MISC
3.3V
Size Size Size Document Number Document Number Document Number
3.3VS 6-71-W54S0-D02A 6-71-W54S0-D02A 6-71-W54S0-D02A
A3 A3 A3 6-7P-W5409-002 6-7P-W5409-002 6-7P-W5409-002
Date: Date: Date: Wednesday, September 25, 2013 Wednesday, September 25, 2013 Wednesday, September 25, 2013 Sheet Sheet Sheet
2 1
1.05V_LAN_M
R301
R312
D
100_1%_04
75_1%_04
100_1%_04
XDP_PREQ#
XDP_TMS
XDP_TDI_R
XDP_TCLK
XDP_TRST#
C
XDP_DBR_R
B
PMSYS_PWRGD_BUF
A
R e v R e v R e v
2.0A 2.0A 2.0A
3 3 3 o f o f o f 45 45 45