MSI MS-6395 Manual page 60

Chapter 3
SDRAM RAS Precharge Time
This item controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to accumu-
late its charge before DRAM refresh, refresh may be incomplete and DRAM
may fail to retain data. This item applies only when synchronous DRAM is
installed in the system. Settings: 3 and 2.
System BIOS Cacheable
System BIOS ROM at F0000h-FFFFFh is always copied to RAM for faster
execution. Selecting Enabled allows the contents of F0000h RAM memory
segment to be written to and read from cache memory, resulting in better
system performance. However, if any program writes to this memory area, a
system error may result. Settings: Enabled and Disabled.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h to
C7FFFh, resulting in better video performance. However, if any program
writes to this memory area, a memory access error may result. Settings:
Enabled and Disabled.
Memory Hole At 15M-16M
In order to improve performance, certain space in memory can be reserved
for ISA peripherals. This memory must be mapped into the memory space
below 16MB. When this area is reserved, it cannot be cached. Settings:
Enabled and Disabled.
CPU Latency Timer
This item allows you to control the GMCH's response to CPU deferrable cycles.
Settings: Disabled and Enabled.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support delayed
transactions cycles so that transactions to and from the ISA bus are buff-
ered and PCI bus can perform other transactions while the ISA transaction is
underway. Select Enabled to support compliance with PCI specification
version 2.1. Settings: Enabled and Disabled.
3-14