Jtag Signal Source Selection; Strapping Pins - Espressif ESP32­-S3 Series Hardware Design Manuallines

2 Schematic Checklist
During the chip's system reset (power-on-reset, RTC watchdog reset, brownout reset, analog super watchdog
reset, and crystal clock glitch detection reset), the latches of the strapping pins sample the voltage level as
strapping bits of "0" or "1", and hold these bits until the chip is powered down or shut down.
GPIO0, GPIO45 and GPIO46 are connected to the chip's internal weak pull-up/pull-down during the chip reset.
Consequently, if they are unconnected or the connected external circuit is high-impedance, the internal weak
pull-up/pull-down will determine the default input level of these strapping pins.
GPIO3 is floating by default. Its strapping value can be configured to determine the source of the JTAG signal
inside the CPU, as shown in Table 4. In this case, the strapping value is controlled by the external circuit that
cannot be in a high impedance state. Table
EFUSE_DIS_USB_JTAG, EFUSE_DIS_PAD_JTAG, and EFUSE_STRAP_JTAG_SEL that determine the JTAG
signal source.
EFUSE_STRAP_JTAG_SEL
1
0
don't care
don't care
don't care
To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or use the host
MCU's GPIOs to control the voltage level of these pins when powering on ESP32-S3.
After reset, the strapping pins work as normal-function pins.
Refer to Table 4 for a detailed configuration of the strapping pins.
Pin
GPIO45
Pin
GPIO0
GPIO46
Enabling/Disabling ROM Messages Print During Booting
Pin
GPIO46
Pin
GPIO3
Espressif Systems
3 shows more configuration combinations of
Table 3: JTAG Signal Source Selection
EFUSE_DIS_USB_JTAG
0
0
0
1
1
Table 4: Strapping Pins
VDD_SPI Voltage
Default 3.3 V
Pull-down 0
Booting Mode
Default SPI Boot
Pull-up 1
Pull-down Don't care
Default Enabled
Pull-down See the fourth note
JTAG Signal Selection
EFUSE_DIS_USB_JTAG = 0, EFUSE_DIS_PAD_JTAG = 0,
Default
EFUSE_STRAP_JTAG_SEL=1
0: JTAG signal from on-chip JTAG pins
N/A
1: JTAG signal from USB Serial/JTAG controller
Submit Documentation Feedback
EFUSE_DIS_PAD_JTAG
0
0
1
0
1
1
1.8 V
1
2
Download Boot
0
0
Disabled
See the fourth note
14
ESP32-S3 Series Hardware Design Guidelines v1.0
JTAG Signal Source
Refer to Table 4
USB Serial/JTAG controller
USB Serial/JTAG controller
On-chip JTAG pins
N/A
3 4