Clock Source; External Clock Source (Compulsory); Schematic For The External Flash And Ram (Psram); Schematic For The Crystal - Espressif ESP32­-S3 Series Hardware Design Manuallines

2 Schematic Checklist
GND

2.4 Clock Source

ESP32-S3 has two clock sources:
• External crystal oscillator clock source
• RTC clock source

2.4.1 External Clock Source (compulsory)

Currently, the ESP32-S3 firmware only supports 40 MHz crystal or oscillator.
Crystal
The circuit for the crystal is shown in Figure 6. The specific capacitive values of C1 and C4 depend on further
testing of, and adjustment to, the overall performance of the whole circuit. In order to reduce the drive strength of
the crystal and minimize the impact of crystal harmonics on RF performance, a zero-ohm series resistor on the
XTAL_P clock trace is required. Note that the accuracy of the selected crystal should be within ±10 ppm.
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
VDD3P3_RTC
XTAL_32K_P
XTAL_32K_N
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
SPICS1
Espressif Systems
C10
0.1uF
GND
42
GPIO37
41
GPIO36
40
GPIO35
39
GPIO34
38
GPIO33
37
SPICLK_P
36
SPICLK_N
35 R16 0
SPID
34
R15 0
SPIQ
33 R10 0
SPICLK
32
SPICS0
31
R14 0
SPIWP
30 R13 0
SPIHD
29
VDD_SPI
C14
C13
0.1uF 1uF
ESP32-S3
GND GND
Figure 5: Schematic for the External Flash and RAM (PSRAM)
3
57
GND
56
VDDA
55
VDDA
54
R4
XTAL_P
53
XTAL_N
52
GPIO46
51
GPIO45
50
U0RXD
49
U0TXD
48
MTMS
47
MTDI
46
VDD3P3_CPU
45
MTDO
44
MTCK
43
GPIO38
Figure 6: Schematic for the Crystal
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VDD33
GPIO37
GPIO36
GPIO35
1
GPIO34 SPICS0
/CS
GPIO33
GPIO47 SPICLK 6
CLK
GPIO48
SPID SPIHD 7
/HOLD
SPIQ
SPICLK
SPICS0 U2
SPIWP
SPIHD
VDD_SPI
SPICS1 1
CS
SPICLK 6
SCLK
SPIHD 7
SIO3
U3
2
0
1
XIN
2
GND
11
ESP32-S3 Series Hardware Design Guidelines v1.0
VDD_SPI
5
SPID
DI
2 SPIQ
DO
3 SPIWP
/WP
FLASH-3V3
GND
VDD_SPI
5 SPID
SI/SIO0
2 SPIQ
SO/SIO1
3 SPIWP
SIO2
(Optional)
PSRAM-3V3
GND
4
GND
3
XOUT
C
B
A
1