Advertisement
Quick Links
Advertisement
Related Manuals for Espressif ESP32-C5
Summary of Contents for Espressif ESP32-C5
- Page 1 ESP32-C5 Hardware Design Guidelines Release master Espressif Systems Apr 23, 2025...
- Page 2 ........25 1.5.1 ESP32-C5 Development Boards ......25 1.5.2...
- Page 4 Table of contents This document provides guidelines for the ESP32-C5 SoC. Schematic Checklist PCB Layout Design Hardware Development Espressif Systems Release master Submit Document Feedback...
- Page 5 Table of contents Espressif Systems Release master Submit Document Feedback...
- Page 6 1.1 About This Document 1.1.1 Introduction The hardware design guidelines advise on how to integrate ESP32-C5 into a product. These guidelines will help to achieve optimal performance of your product, ensuring technical accuracy and adherence to Espressif’s standards. The guidelines are intended for hardware and application engineers.
- Page 7 The integrated circuitry of ESP32-C5 requires only 30 electrical components (resistors, capacitors, and inductors) and a crystal, as well as an SPI flash. The high integration of ESP32-C5 allows for simple peripheral circuit design. This chapter details the schematic design of ESP32-C5.
- Page 8 Digital Power Supply ESP32-C5 has VDDPST1 (pin8), VDDPST2 (pin24), and VDDPST3 (pin39) as the digital power supply pin(s) working in a voltage range of 3.0 V ~ 3.6 V. It is recommended to add an extra 1 μF decoupling capacitor close to VDDPST1, and an extra 0.1 μF decoupling capacitor close to VDDPST2 and VDDPST3.
- Page 9 1.3.3 Chip Power-up and Reset Timing ESP32-C5’s CHIP_PU pin can enable the chip when it is high and reset the chip when it is low. When ESP32-C5 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_PU is pulled up and the chip is enabled.
- Page 10 SPIHD SIO3 Off-Package Flash and PSRAM ESP32-C5 supports up to 32 MB off-package flash and PSRAM. It is recommended to add zero-ohm resistor foot- prints in series on the SPI communication lines as shown in Figure ESP32-C5 Schematic for External Flash/PSRAM.
- Page 11 External crystal clock source (Compulsory) • RTC clock source (Optional) External Crystal Clock Source (Compulsory) The ESP32-C5 firmware only supports 48 MHz crystal. The circuit for the crystal is shown in Figure ESP32-C5 Schematic for External Crystal. Note that the accuracy of the selected crystal should be within ±10 ppm.
- Page 12 RTC Clock Source (Optional) ESP32-C5 supports an external 32.768 kHz crystal to act as the RTC clock. The external RTC clock source enhances timing accuracy and consequently decreases average power consumption, without impacting functionality. Figure ESP32-C5 Schematic for 32.768 kHz Crystal...
- Page 13 Chapter 1. Latest Version of This Document RF Circuit ESP32-C5’s RF circuit is mainly composed of three parts, the RF traces on the PCB board, the chip matching circuit, the antenna and the antenna matching circuit. Each part should meet the following requirements: •...
- Page 14 Note: If RF function is not required, then the RF pin can be left floating. 1.3.7 UART ESP32-C5 includes three UART interfaces, UART0, UART1, and LP UART, all of which support both hardware flow control (CTS and RTS signals) and software flow control (XON and XOFF).
- Page 15 GPIO25, GPIO26, GPIO27, GPIO28, GPIO7, MTMS, and MTDI are strapping pins. All the information about strapping pins is covered in ESP32-C5 Series Datasheet > Chapter Boot Configurations. In this document, we will mainly cover the strapping pins related to boot mode.
- Page 16 Do not add high-value capacitors at GPIO28, or the chip may enter download mode. 1.3.10 GPIO The pins of ESP32-C5 can be configured via IO MUX or GPIO matrix. IO MUX provides the default pin configura- tions (see ESP32-C5 Series Datasheet >...
- Page 17 Please add a 0.1 μF filter capacitor between ESP pins and ground when using the ADC function to improve accuracy. ADC functions are shown in the table below. Table 9: ADC Functions Pin No IO Pin Name ADC Function GPIO1 ADC1_CH0 GPIO2 ADC1_CH1 GPIO3 ADC1_CH2 GPIO4 ADC1_CH3 GPIO5 ADC1_CH4 GPIO6 ADC1_CH5 Espressif Systems Release master Submit Document Feedback...
- Page 18 ESP32-C5 also supports download functions and log message printing via USB. For details please refer to Section Download Guidelines. 1.4 PCB Layout Design This chapter introduces the key points of how to design an ESP32-C5 PCB layout using an ESP32-C5 module (see Figure ESP32-C5 Reference PCB Layout) as an example.
- Page 19 PCB design. Fig. 12: ESP32-C5 Power Traces in a Four-layer PCB Design • Whenever possible, route the power traces on the inner layers (not the ground layer) and connect them to the chip pins through vias.
- Page 20 See the figure below. Fig. 13: ESP32-C5 Power Traces for Pins 40 and 41 • Place appropriate decoupling capacitors at the rest of the power pins. Ground vias should be added close to the capacitor’s ground pad to ensure a short return path.
- Page 21 Chapter 1. Latest Version of This Document Fig. 14: ESP32-C5 EPAD Design at Chip Bottom Fig. 15: ESP32-C5 Crystal Layout (with Keep-out Area on Top Layer) Espressif Systems Release master Submit Document Feedback...
- Page 22 ESP32-C5 RF Layout in a Four-layer PCB Design. Fig. 16: ESP32-C5 RF Layout in a Four-layer PCB Design The RF layout should meet the following guidelines: • A CLC matching circuit should be added to the RF trace. Please use 0201 components and place them close to the pin in a zigzag.
- Page 23 Chapter 1. Latest Version of This Document Fig. 17: ESP32-C5 PCB Stack-up Design Fig. 18: ESP32-C5 Stub in a Four-layer PCB Design Espressif Systems Release master Submit Document Feedback...
- Page 24 Chapter 1. Latest Version of This Document Fig. 19: ESP32-C5 IPEX Layout • The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace should be routed at a 135° angle, or with circular arcs if trace bends are required.
- Page 25 Chapter 1. Latest Version of This Document Fig. 20: ESP32-C5 Quad SPI Flash Layout Fig. 21: ESP32-C5 UART Layout Espressif Systems Release master Submit Document Feedback...
- Page 26 Fig. 22: Placement of ESP32-C5 Modules on Base Board (antenna GND point on the right) If the PCB antenna cannot be placed outside the board, please ensure a clearance of at least 15 mm around the antenna area (no copper, routing, or components on it), and place the GND point of the antenna closest to the board.
- Page 27 Crystal for details. When ESP32-C5 sends data packages, the power value is much higher or lower than the target power value, and the EVM is relatively poor. Analysis: The disparity between the tested value and the target value may be due to signal reflection caused by the impedance mismatch on the transmission line connecting the RF pin and the antenna.
- Page 28 • .pcb files: Pads Layout VX.2. If you cannot open the .pcb files, please try importing the .asc files into your software to view the PCB layout. 1.5.1 ESP32-C5 Development Boards For a list of the latest designs of ESP32-C5 boards please check the Development Boards section on Espressif’s official website.
- Page 29 A zero-ohm resistor acts as a placeholder in the circuit, allowing for the replacement with a higher-ohm resistor based on specific design requirements. 1.8 Revision History This is the first release of the ESP32-C5 Hardware Design Guidelines. Espressif Systems Release master...
- Page 30 The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG. All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are hereby acknowledged. Espressif Systems Release master Submit Document Feedback...
Need help?
Do you have a question about the ESP32-C5 and is the answer not in the manual?
Questions and answers