2 Schematic Checklist
The rest of this document details the specifics of circuit design for each of these sections.
2.1 Power Supply
Details of using power supply pins can be found in Section Power Scheme in
2.1.1 Digital Power Supply
ESP32-S3 has pin46 VDD3P3_CPU that supplies power to CPU IO, in a voltage range of 3.0 V
recommended to add an extra 0.1 µF decoupling capacitor close to each digital power supply pin.
Pin29 VDD_SPI can serve as the power supply for the external device at either 1.8 V if GPIO45 is pulled high
during boot, or at 3.3 V if GPIO45 is pulled low during boot. It is recommended to add extra 0.1 µF and 1 µF
decoupling capacitors close to VDD_SPI.
4
• When VDD_SPI operates at 1.8 V, it is powered by the internal Flash Voltage Regulator on the chip. The
maximum current this Flash Voltage Regulator can offer is 40 mA.
GND
• When VDD_SPI operates at 3.3 V, it is driven directly by VDD3P3_RTC through R
there will be some voltage drop from VDD3P3_RTC.
C1
VDD_SPI can also be driven by an external power supply.
TBD
Notice:
When using VDD_SPI as the power supply pin for the external 3.3 V flash/PSRAM, the supply voltage should be 3.0 V or
GND
40MHz(±10ppm)
above, so as to meet the requirements of flash/PSRAM's working voltage.
C2
10nF
The schematic for the digital power supply pins is shown in Figure 2.
GND
GND
2.0nH
C9
GND
LNA_IN
1
TBD
LNA_IN
2
VDD3P3
3
C12
VDD3P3
CHIP_PU
4
CHIP_PU
TBD
GPIO0
5
GPIO0
6
GPIO1
GPIO1
GPIO2
7
GPIO2
GPIO3
8
GND
GPIO3
GPIO4
9
GPIO4
GPIO5
10
GPIO5
GPIO6
11
GPIO6
GPIO7
12
GPIO7
GPIO8
13
GPIO8
14
GPIO9
GPIO9
U1
VDD33
C15
0.1uF
GND
Espressif Systems
GND
GND
Y1
C4
TBD
Figure 2: Schematic for the Digital Power Supply Pins
3
VDD33
R1
10K(NC)
R3
C10
0.1uF
GND
42
GPIO37
41
GPIO36
40
GPIO35
39
GPIO34
38
GPIO33
37
SPICLK_P
36
SPICLK_N
35
R16
SPID
34
R15
SPIQ
33
R10
SPICLK
32
SPICS0
31
R14
SPIWP
30
R13
SPIHD
29
VDD_SPI
C13
0.1uF
ESP32-S3
GND
GND
7
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ESP32-S3 Series
2
SP I
GPIO46
GPIO45
U0RXD
499
U0TXD
GPIO42
GPIO41
GPIO40
GPIO39
GPIO38
VDD33
GPIO37
GPIO36
GPIO35
GPIO34
SPICS0
1
GPIO33
6
GPIO47
SPICLK
GPIO48
SPID
SPIHD
7
0
0
SPIQ
0
SPICLK
SPICS0
U2
0
SPIWP
0
SPIHD
C14
VDD_SPI
1uF
SPICS1
1
SPICLK
6
SPIHD
7
U3
ESP32-S3 Series Hardware Design Guidelines v1.0
Datasheet.
~
3.6 V. It is
resistor, therefore,
VDD_SPI
5
SPID
/CS
DI
2
SPIQ
CLK
DO
3
SPIWP
/HOLD
/WP
FLASH-3V3
GND
VDD_SPI
5
SPID
CS
SI/SIO0
2
SPIQ
SCLK
SO/SIO1
3
SPIWP
SIO3
SIO2
(Optional)
PSRAM-3V3
GND
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