Processor 7/7 - EUROCOM P150HM Series Service Manual

Processor 7/7

Sandy Bridge Processor 7/7 ( RESERVED )
CFG Straps for Processor
PEG Static Lane Reve rsal - CF G2 is for the 16x
CFG2
C F G 2
R 8 3
Display Port Presenc e Strap
CFG4
C F G 4 R 8 1
3 . 3 V
PCIE Port Bifurcatio n Straps
R 3 1 2
1 00 K _ 0 4
CFG[6:5]
H _S N B _ I V B #_ P W R C TR L
C F G 5 R 7 7
C F G 6 R 7 4
PEG DEFER TRAINING
CFG7
C F G 7 R 7 3
1. 5 V
R 3 5 3 *0 _ 0 4
R 3 6 2
Q 25 1 K _ 1 % _ 0 4
* A O3 4 0 2L
H _ C P U _ R S V D 6 S D
R 3 3 9 R 3 3 2
*1 K _ 0 4
1 K _ 1 % _ 0 4
D R A M R S T _ C N T R L 4 , 2 0
R 3 75 *0 _ 0 4
Q2 6
*A O 3 4 02 L
H _C P U _ R S V D 7 S D
R 3 70
* 1K _0 4
D R A MR S T _ C N T R L 4 , 2 0
1:(Default) N ormal Oper ation; La ne #
definition ma tches sock et pin ma p definition
0:Lane Revers ed
* 1 K _ 04
1:(Default) D isabled; N o Physica l Display Port
attached to E mbedded Di splay Por t
0:Enabled; An external Display P ort device is
connected to the Embedd ed Displa y Port
* 1 K _ 04
11: ( Default) x16 - Device 1 func tions 1 a nd 2 disa bled
10: x 8, x8 - D evice 1 function 1 enabled ; function 2 disabl ed
01: R eserved - (Device 1 function 1 disabl ed ; func tion 2 en abled)
00: x 8,x4,x4 - Device 1 functions 1 and 2 enabled
* 1 K _ 04
* 1 K _ 04
1: (Default) PEG Train immediate ly following xxRES ETB de ass ertion
0: PEG Wait f or BIOS fo r trainin g
* 1 K _ 04
H _ S N B _ I V B #_ P W R C T R L R 31 3
On CRB
H_SNB_IVB# _PWRCTRL = low, 1.0 V
H_SNB_IVB# _PWRCTRL = high/NC, 1.05V
R 35 2 0_ 0 4
MV R E F _ D Q_ D I MM A 1 0 , 1 1
R 36 0 *0 _ 04
MV R E F _ C A _ D I M MA 10
1 . 5 V
R 3 6 9
1 K _ 1% _ 0 4
R 3 8 0 0 _ 0 4
M V R E F _ D Q _D I M MB 1 2 , 1 3
R 3 7 4 * 0 _0 4
M V R E F _ C A _ D I MM B 1 2
R 3 8 2
1 K _ 1% _ 0 4
U 32 E
R S V D 2 8
A K 2 8 R S V D 2 9
C F G[ 0 ] R S V D 3 0
A K 2 9
C F G[ 1 ] R S V D 3 1
C F G 2 A L 2 6
C F G[ 2 ] R S V D 3 2
A L 2 7
C F G[ 3 ]
C F G 4 A K 2 6
A L 2 9 C F G[ 4 ]
C F G 5
C F G[ 5 ] R S V D 3 3
C F G 6 A L 3 0
C F G[ 6 ] R S V D 3 4
C F G 7 A M 3 1
C F G[ 7 ] R S V D 3 5
A M 3 2
C F G[ 8 ]
A M 3 0
A M 2 8 C F G[ 9 ]
C F G[ 1 0 ]
A M 2 6
C F G[ 1 1 ]
A N 2 8
A N 3 1 C F G[ 1 2 ]
C F G[ 1 3 ] R S V D 3 7
A N 2 6
C F G[ 1 4 ] R S V D 3 8
A M 2 7
C F G[ 1 5 ] R S V D 3 9
A K 3 1
C F G[ 1 6 ] R S V D 4 0
A N 2 9
C F G[ 1 7 ]
R S V D 4 1
A J 3 1
A H 3 1 R S V D 1 R S V D 4 2
R S V D 2 R S V D 4 3
A J 3 3
R S V D 3 R S V D 4 4
A H 3 3
R S V D 4 R S V D 4 5
A J 2 6
R S V D 5
R S V D 4 6
H _ C P U _ R S V D 6 B 4
R S V D 6 R S V D 4 7
H _ C P U _ R S V D 7 D 1
R S V D 7 R S V D 4 8
R S V D 4 9
R S V D 5 0
F 2 5
R S V D 8
F 2 4
F 2 3 R S V D 9
R S V D 1 0
D 2 4
R S V D 1 1 R S V D 5 1
G 2 5
R S V D 1 2 R S V D 5 2
G 2 4
R S V D 1 3
E 2 3
D 2 3 R S V D 1 4
R S V D 1 5
C 3 0
R S V D 1 6 R S V D 5 3
A 3 1
R S V D 1 7
B 3 0
R S V D 1 8
B 2 9
D 3 0 R S V D 1 9
R S V D 2 0 R S V D 5 4
B 3 1
R S V D 2 1 R S V D 5 5
A 3 0
C 2 9 R S V D 2 2
R S V D 2 3
J 2 0
R S V D 2 4
B 1 8
A 1 9 R S V D 2 5 R S V D 5 6
0 _ 0 4
R S V D 2 6 R S V D 5 7
R S V D 5 8
J 1 5
R S V D 2 7
K E Y
P Z 9 8 9 2 7- 36 4 1 -0 1F
3 . 3 V 3 , 4 , 1 4 , 15 , 1 9 , 2 0 , 2 1, 2 3 , 2 4 , 2 5, 26 , 2 8 , 2 9 , 30 , 3 2 , 3 5 , 3 6, 3 7 , 3 9 , 4 0, 41 , 4 2
1 . 5 V 4 , 1 0 , 1 1, 1 2 , 1 3 , 2 6, 30 , 3 7 , 3 9 , 41
Schematic Diagrams
L 7
A G7
A E 7
A K 2
W 8
A T 2 6
A M3 3
A J 2 7
T 8
J 16
H 1 6
G1 6
Sheet 8 of 58
A R 3 5
A T 3 4
A T 3 3 Processor 7/7
A P 3 5
A R 3 4
B 3 4
A 3 3
A 3 4
B 3 5
C 3 5
A J 3 2
A K 3 2
A H 2 7
A N 3 5
A M3 5
A T 2
A T 1
A R 1
B 1
Processor 7/7 B - 9