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Infineon TLE9262-3BQX Manual

Infineon TLE9262-3BQX Manual

Mid-range+ system basis chip family
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TLE9262-3BQX
System Basis Chip
Mid-Range+ System Basis Chip Family
Quality Requirement Category: Automotive
Features
•
Two integrated Low-Drop Voltage Regulators: Main regulator (5 V or 3.3 V
up to 250 mA) and auxiliary regulator (5 V up to 100 mA) with off-board
usage protection
•
Voltage regulator (5 V, 3.3 V or 1.8 V) with external PNP transistor configurable for off-board usage or for
load sharing
•
1 high-speed CAN transceiver supporting FD communication up to 5 Mbit/s featuring CAN Partial
Networking & CAN FD tolerant mode according to ISO 11898-2:2016 & SAE J2284
•
LIN transceiver LIN2.2A/J2602
•
4 high-side outputs 7 Ω typ., 2 HV GPIOs, 3 HV wake inputs
•
Integrated fail-safe and supervision functions, e.g. fail-safe, watchdog, interrupt- and reset outputs
•
16-bit SPI for configuration and diagnostics
Applications
•
Body Control Modules (BMC), Passive keyless entry and start modules, Gateway applications
•
Heating, ventilation and air conditioning (HVAC)
•
Seat, roof, tailgate, trailer, door and other closure modules
•
Light control modules
•
Gear shifters and selectors
Description
Body System IC with Integrated Voltage Regulators, Power Management Functions, HS-CAN Transceiver
supporting CAN FD featuring Partial Networking (incl. FD Tolerant Mode) and LIN Transceiver.
Featuring Multiple High-Side Switches and High-Voltage Wake Inputs.
Type
TLE9262-3BQX
Data Sheet
www.infineon.com
Arrow.com.
Downloaded from
Package
PG-VQFN-48-31
1
Marking
TLE9262-3BQX
Rev. 1.00
2017-07-31

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Do you have a question about the TLE9262-3BQX and is the answer not in the manual?

Questions and answers

Georgeta Dobriceanu
April 1, 2025

I want to know howto set the LIN tranceiver in NORMAL Mode

0
1 comments:
Mr. Anderson
April 1, 2025

To set the Infineon TLE9262-3BQX LIN transceiver in NORMAL mode, follow these steps:

1. Ensure the transceiver is out of Sleep Mode. If waking from Sleep Mode, the RXD pin is set to LOW, and the microcontroller can read the wake source from the WK_STAT_1 register via SPI.

2. Use SPI communication from the microcontroller to switch the transceiver into LIN NORMAL mode.

3. Wait for the enabling time (tLIN,EN) before sending a message. The TXDLIN signal should be pulled LOW only after this time.

4. If TXDLIN is pulled LOW too early, set it back to HIGH (recessive) and wait until the enabling time is completed before transmitting.

This ensures proper LIN bus communication.

This answer is automatically generated

0

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Summary of Contents for Infineon TLE9262-3BQX

  • Page 1 TLE9262-3BQX System Basis Chip Mid-Range+ System Basis Chip Family Quality Requirement Category: Automotive Features • Two integrated Low-Drop Voltage Regulators: Main regulator (5 V or 3.3 V up to 250 mA) and auxiliary regulator (5 V up to 100 mA) with off-board usage protection •...

  • Page 2: Table Of Contents

    TLE9262-3BQX Table of Contents Overview ............... . 6 Block Diagram .
  • Page 3 TLE9262-3BQX 5.4.3.8 CAN Bus Timeout-Flag (CANTO) ............48 5.4.3.9...
  • Page 4 TLE9262-3BQX 10.2 Functional Description ..............85 10.2.1...
  • Page 5 TLE9262-3BQX 15.2.4 Watchdog during SBC Stop Mode ............131 15.2.5...

  • Page 6: Overview

    CAN Partial Networking variants for 5V (TLE926x-3QX) and 3.3V (TLE926x-3QXV33) output voltage Device Description The TLE9262-3BQX is a monolithic integrated circuit in an exposed pad VQFN-48 (7mm x 7mm) power package with Lead Tip Inspection (LTI) feature to support Automatic Optical Inspection (AOI).
  • Page 7 TLE9262-3BQX Overview Product Features • Very low quiescent current consumption in Stop- and Sleep Mode • Periodic Cyclic Wake in SBC Normal- and Stop Mode • Periodic Cyclic Sense in SBC Normal-, Stop- and Sleep Mode • Low-Drop Voltage Regulator 5V, 250mA •...

  • Page 8: Block Diagram

    TLE9262-3BQX Block Diagram Block Diagram VSHS High Side VCC2 FO3/TEST Fail Safe Alternative function for FO2/3: GPIO 1/2 STATE MACHINE Interrupt Control Window Watchdog RESET GENERATOR VCAN Alternative function for WK 1/2: WAKE Voltage measurement TXDCAN REGISTER RXDCAN CAN cell...

  • Page 9: Pin Configuration

    TLE9262-3BQX Pin Configuration Pin Configuration Pin Assignment VCAN 37 24 WK3 GND 38 23 WK2 CANL 39 22 WK1 CANH 40 21 FO1 n.c. 41 TLE9262 20 GND LIN1 42 19 n.c. GND 43 18 VCC2 PG-VQFN-48 N.U. 44 17 VCC1 n.c.

  • Page 10: Pin Definitions And Functions

    TLE9262-3BQX Pin Configuration Pin Definitions and Functions Symbol Function Ground n.c. not connected; internally not bonded. VCC3REF VCC3REF; Collector connection for external PNP, reference input VCC3B VCC3B; Base connection for external PNP VCC3SH VCC3SH; Emitter connection for external PNP, shunt connection n.c.
  • Page 11 TLE9262-3BQX Pin Configuration Symbol Function SPI Chip Select Not Input Interrupt Output; used as wake-up flag for microcontroller in SBC Stop or Normal Mode and for indicating failures. Active low. During start-up used to set the SBC configuration. External pull-up sets config 1/3, no external pull-up sets config 2/4.

  • Page 12: Hints For Unused Pins

    TLE9262-3BQX Pin Configuration Hints for Unused Pins It must be ensured that the correct configurations are also selected, i.e. in case functions are not used that they are disabled via SPI: • WK1/2/3: connect to GND and disable WK inputs via SPI •...

  • Page 13: General Product Characteristics

    TLE9262-3BQX General Product Characteristics General Product Characteristics Absolute Maximum Ratings Table 1 Absolute Maximum Ratings = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note /...
  • Page 14 TLE9262-3BQX General Product Characteristics Table 1 Absolute Maximum Ratings (cont’d) = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note / Number Test Condition Min.

  • Page 15: Functional Range

    TLE9262-3BQX General Product Characteristics Functional Range Table 2 Functional Range Parameter Symbol Values Unit Note / Number Test Condition Min. Typ. Max. Supply Voltage – P_4.2.1 S,func section Chapter 15.10 LIN Bus Voltage – P_4.2.2 S,LIN,func CAN Supply Voltage 4.75 –...

  • Page 16: Thermal Resistance

    TLE9262-3BQX General Product Characteristics Thermal Resistance Table 3 Thermal Resistance Parameter Symbol Values Unit Note / Number Test Condition Min. Typ. Max. Junction to Soldering Point – – Exposed Pad P_4.3.1 thJSP Junction to Ambient – – P_4.3.2 thJA 1) Not subject to production test, specified by design.

  • Page 17: Current Consumption

    TLE9262-3BQX General Product Characteristics Current Consumption Table 4 Current Consumption Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max.
  • Page 18 TLE9262-3BQX General Product Characteristics Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Feature Incremental Current Consumption Current consumption for CAN –...
  • Page 19 TLE9262-3BQX General Product Characteristics Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. Current consumption per LIN –...
  • Page 20 TLE9262-3BQX General Product Characteristics Table 4 Current Consumption (cont’d) Current consumption values are specified at Tj = 25°C, VS = 13.5V, all outputs open (unless otherwise specified) Parameter Symbol Values Unit Note / Test Condition Number Min. Typ. Max. 1)5) Current consumption for –...
  • Page 21 TLE9262-3BQX General Product Characteristics 6) No pull-up or pull-down configuration selected. 7) The specified WKx current consumption adder for wake capability applies regardless how many WK inputs are activated. 8) A typ. 75µA / max 125µA ( = 85°C) adder applies for every additionally activated HSx switch in SBC Stop Mode;...

  • Page 22: System Features

    TLE9262-3BQX System Features System Features This chapter describes the system features and behavior of the TLE9262-3BQX: • State machine • SBC mode control • Device configuration • State of supply and peripherals • System functions such as cyclic sense or cyclic wake •...

  • Page 23: Block Description Of State Machine

    TLE9262-3BQX System Features Block Description of State Machine The different SBC Modes are selected via SPI by setting the respective SBC MODE bits in the register M_S_CTRL. The SBC MODE bits are cleared when going through SBC Restart Mode and thus always show the current SBC mode.

  • Page 24: Device Configuration And Sbc Init Mode

    TLE9262-3BQX System Features 5.1.1 Device Configuration and SBC Init Mode The SBC starts up in SBC Init Mode after crossing the power-on reset threshold (see also Chapter 15.3) POR,r and the watchdog will start with a long open window During this power-on phase following configurations are stored in the device: •...
  • Page 25 TLE9262-3BQX System Features POR,r VCC1 RT1,r Continuous Filtering with CFG_F Configuration selection monitoring period Figure 4 Hardware Configuration Selection Timing Diagram There are four different device configurations (Table 5) available defining the watchdog failure and the VCC1 overvoltage behavior. The configurations can be selected via the external connection on the INT pin and the...
  • Page 26 TLE9262-3BQX System Features Table 6 shows the configurations and the device behavior in case of a VCC1 overvoltage detection when VCC1_OV_RST is set: Table 6 Device Behavior in Case of VCC1 Overvoltage Detection Config INT Pin (CFGP) VCC1_O Event VCC1_...

  • Page 27: Sbc Init Mode

    TLE9262-3BQX System Features 5.1.1.2 SBC Init Mode In SBC Init Mode, the device waits for the microcontroller to finish its startup and initialization sequence. In the SBC Init Mode any valid SPI command will bring the SBC to SBC Normal Mode. During the long open window the watchdog has to be triggered.

  • Page 28: Sbc Normal Mode

    TLE9262-3BQX System Features 5.1.2 SBC Normal Mode The SBC Normal Mode is the standard operating mode for the SBC. All configurations have to be done in SBC Normal Mode before entering a low-power mode (see also Chapter 5.1.6 for the device configuration defining the Fail-Safe Mode behavior).

  • Page 29: Sbc Stop Mode

    TLE9262-3BQX System Features 5.1.3 SBC Stop Mode The SBC Stop Mode is the first level technique to reduce the overall current consumption by setting the voltage regulators VCC1, VCC2 and VCC3 into a low-power mode. In this mode VCC1 is still active and supplying the microcontroller, which can enter a power down mode.

  • Page 30: Sbc Sleep Mode

    TLE9262-3BQX System Features 5.1.4 SBC Sleep Mode The SBC Sleep Mode is the second level technique to reduce the overall current consumption to a minimum needed to react on wake-up events or for the SBC to perform autonomous actions (e.g. cyclic sense). In this mode, VCC1 is OFF and not supplying the microcontroller anymore.The VCC2 supply as well as the HSx outputs...

  • Page 31: Sbc Restart Mode

    TLE9262-3BQX System Features 5.1.5 SBC Restart Mode There are multiple reasons to enter the SBC Restart Mode. The purpose of the SBC Restart Mode is to reset the microcontroller: • in case of undervoltage on VCC1 in SBC Normal and in SBC Stop Mode,...

  • Page 32: Sbc Fail-Safe Mode

    TLE9262-3BQX System Features Note: An overvoltage event on VCC1 will only lead to SBC Restart Mode if the bit VCC1_OV_RST is set and if CFGP = ‘1’ (Config 1/3). Note: The content of the WD_FAIL bits will depend on the device configuration, e.g. 1 or 2 watchdog failures.

  • Page 33: Sbc Development Mode

    TLE9262-3BQX System Features Table 8 Reasons for Fail-Safe - State of SPI Status Bits after Return to Normal Mode Prev. SBC Failure Event DEV_ TSD2 VCC1_ VCC1_ VCC1_ VCC1_ Mode STAT FAIL UV_FS Normal 1 x Watchdog Failure 01 Normal...
  • Page 34 TLE9262-3BQX System Features Note: The absolute maximum ratings of the pin FO3/TEST must be observed. To increase the robustness of this pin during debugging or programming a series resistor between FO3/TEST and the connector can be added (see Figure 66).

  • Page 35: Wake Features

    TLE9262-3BQX System Features Wake Features Following wake sources are implemented in the device: Chapter 12 • Static Sense: WK inputs are permanently active (see • Cyclic Sense: WK inputs only active during on-time of cyclic sense period (see below) •...

  • Page 36: Configuration And Operation Of Cyclic Sense

    TLE9262-3BQX System Features 5.2.1.1 Configuration and Operation of Cyclic Sense The correct sequence to configure the cyclic sense is shown in Figure 6. All the configurations have to be performed before the on-time is set in the TIMERx_CTRL registers. The settings “OFF / LOW” and “OFF / HIGH”...
  • Page 37 TLE9262-3BQX System Features The first sample of the WK input value (HIGH or LOW) is taken as the reference for the next cycle. A change of the WK input value between the first and second cycle recognized during the on-time of the second cycle will cause a wake from SBC Sleep Mode or an interrupt during SBC Normal or SBC Stop Mode.
  • Page 38 TLE9262-3BQX System Features A wake event due to cyclic sense will set the respective bit WK1_WU, WK2_WU, or WK3_WU. During Cyclic Sense, WK_LVL_STAT is updated only with the sampled voltage levels of the WKx pins in SBC Normal or SBC Stop Mode.

  • Page 39: Cyclic Sense In Low Power Mode

    TLE9262-3BQX System Features Filter time High Switch Spike open closed High = WK = Low (but ignored because = High Learning = Low ≠WK change during filter time ) Cycle = WK = WK wake event = Low no wake event...

  • Page 40: Cyclic Wake

    TLE9262-3BQX System Features 5.2.2 Cyclic Wake The cyclic wake feature is intended to reduce the quiescent current of the device and application. For the cyclic wake feature one or both timers are configured as internal wake-up source and will periodically trigger an interrupt in SBC Normal and SBC Stop Mode.

  • Page 41: Internal Timer

    TLE9262-3BQX System Features 5.2.3 Internal Timer The integrated Timer1 and Timer2 are typically used to wake up the microcontroller periodically (cyclic wake) or to perform cyclic sense on the wake inputs. Therefore, the timers can be mapped to the dedicated HS switches by SPI (via HS_CTRL1...2).

  • Page 42: Partial Networking On Can

    TLE9262-3BQX Partial Networking on CAN 5.4.1 CAN Partial Networking - Selective Wake Feature The CAN Partial Networking feature can be activated for SBC Normal Mode, in SBC Sleep Mode and in SBC Stop Mode. For SBC Sleep Mode the Partial Networking has to be activated before sending the SBC to Sleep Mode.

  • Page 43: Sbc Partial Networking Function

    TLE9262-3BQX 5.4.2 SBC Partial Networking Function The CAN Partial Networking Modes are shown in this figure. CAN WK Mode CAN Receive Only without PN Mode Normal Mode CAN PN Config Check Enable/ Disable max. 4 CAN Wakable Mode CAN frames...

  • Page 44: Activation Of Swk

    TLE9262-3BQX 5.4.2.1 Activation of SWK Below figure shows the principal of the SWK activation. SBC Normal Mode SW not enabled CAN OFF Enabling CAN (not OFF) enables also the selective wake block. Block gets SYNC = 1 synchronous to the CAN bus.

  • Page 45: Wake-Up Pattern (Wup)

    TLE9262-3BQX 5.4.2.2 Wake-up Pattern (WUP) A WUP is signaled on the bus by two consecutive dominant bus levels for at least t , each separated by a Wake1 recessive bus level. Entering low -power mode , when selective wake-up function is disabled Bus recessive >...

  • Page 46: Can Protocol Error Counter

    TLE9262-3BQX • In case DLC is greater than 0, the data field of the received frame has at least one bit set in a bit position, where also in the configured data mask in the corresponding bit position the bit is set.

  • Page 47: Diagnoses Flags

    TLE9262-3BQX 5.4.3 Diagnoses Flags 5.4.3.1 PWRON/RESET-FLAG The power-on reset can be detected and read by the bit in the SBC Status register. The VS power on resets all register in the SBC to reset value. SWK is not configured. 5.4.3.2 BUSERR-Flag Bus Dominant Time-out detection is implemented and signaled by CAN_Fail_x in register BUS_STAT_1.

  • Page 48: Can Bus Timeout-Flag (Canto)

    TLE9262-3BQX detect a Configuration Error while SWK is enabled. This will occur if the CFG_VAL bit is cleared, e.g. by changing the SWK registers (from address 010 0001 to address 011 0011). In SBC Stop Mode and SBC Sleep Mode this is not possible as the SWK registers can not be changed.
  • Page 49 TLE9262-3BQX • after a wake-up (ECNT overflow, WUP in WUP detection 2, WUF in WUF detection) • if CAN_2 is cleared Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 50: Sbc Modes For Selective Wake (Swk)

    TLE9262-3BQX 5.4.4 SBC Modes for Selective Wake (SWK) The SBC mode is selected via the MODE bits as described in Chapter 5.1. The mode of the CAN transceiver needs to be selected in SBC Normal Mode. The CAN mode is programed the bits CAN_0, CAN_1 and CAN_2.

  • Page 51: Sbc Stop Mode With Swk

    TLE9262-3BQX monitors the data on the CAN bus, updates the error counter and sets the CANSIL flag if there is no communication on the bus. It will generate an CAN Wake interrupt in case a WUF is detected (RXD is not pulled to LOW in this configuration).

  • Page 52: Sbc Sleep Mode With Swk

    TLE9262-3BQX Table 10 CAN Modes change when switching from SBC Normal Mode to SBC Stop Mode Programmed CAN Mode in SBC CAN_x SYSERR CAN Mode in SBC Stop Mode CAN_x Normal Mode bits bits CAN OFF CAN OFF CAN WK Mode (no SWK)

  • Page 53: Sbc Restart Mode With Swk

    TLE9262-3BQX Table 11 CAN Modes change when switching to SBC Sleep Mode Programmed CAN Mode in SBC CAN_x SYSERR CAN Mode in SBC Sleep Mode CAN_x Normal Mode bits bits CAN OFF CAN OFF CAN WK Mode (no SWK) CAN WK Mode (no SWK)

  • Page 54: Sbc Fail-Safe Mode With Swk

    TLE9262-3BQX Table 13 CAN Modes change in case of Restart out of SBC Sleep Mode CAN Mode in SBC CAN Mode in CAN_ CAN_ WUP WUF ECNT_ Reason for Restart Sleep Mode and after SBC Restart Mode CAN OFF CAN OFF...
  • Page 55 TLE9262-3BQX The actual configuration for selective wake is done via the Selective Wake Control Registers SWK_IDx_CTRL, SWK_MASK_IDx_CTRL, SWK_DLC_CTRL, SWK_DATAx_CTRL. The oscillator has the option to be trimmed by the microcontroller. To measure the oscillator, the SPI bit OSC_CAL needs to be set to 1 and a defined pulse needs to be given to the TXDCAN pin by the microcontroller (e.g.

  • Page 56: Can Flexible Data Rate (Can Fd) Tolerant Mode

    TLE9262-3BQX 5.4.7 CAN Flexible Data Rate (CAN FD) Tolerant Mode The CAN FD tolerant mode can be activated by setting the bit CAN_FD_ EN = ‘1’ in the register SWK_CAN_FD_CTRL. With this mode the internal CAN frame decoding will be stopped for CAN FD frame formats: •...

  • Page 57: Clock And Data Recovery

    TLE9262-3BQX 5.4.8 Clock and Data Recovery In order to compensate possible deviations on the CAN oscillator frequency caused by assembly and lifetime effects, the device features an integrated clock and data recovery (CDR). It is recommended to always enable the CDR feature during SWK operation.

  • Page 58: Setup Of Clock And Data Recovery

    TLE9262-3BQX 5.4.8.2 Setup of Clock and Data Recovery It is strongly recommended to enable the clock and data recovery feature only when the setup of the clock and data recovery is finished. The following sequence should be followed for enabling the clock and data recovery feature: •...

  • Page 59: Electrical Characteristics

    TLE9262-3BQX 5.4.9 Electrical Characteristics Table 15 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; 4.75 V < VCAN < 5.25 V; RL = 60Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin...

  • Page 60: Voltage Regulator 1

    TLE9262-3BQX Voltage Regulator 1 Voltage Regulator 1 Block Description V CC1 Vref Overtemperature Shutdown State Machine Bandgap Reference Figure 16 Module Block Diagram Functional Features 5V low-drop voltage regulator • Undervoltage monitoring with adjustable reset level, VCC1 prewarning and VCC1 short circuit detection •...

  • Page 61: Functional Description

    TLE9262-3BQX Voltage Regulator 1 Functional Description The Voltage Regulator 1 (=VCC1) is “ON” in SBC Normal and SBC Stop Mode and is disabled in SBC Sleep and in SBC Fail-Safe Mode. The regulator can provide an output current up to I...

  • Page 62: Electrical Characteristics

    TLE9262-3BQX Voltage Regulator 1 Electrical Characteristics Table 16 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Values Parameter Symbol...
  • Page 63 TLE9262-3BQX Voltage Regulator 1 2) Not subject to production test, specified by design. Figure 17 Typical on-resistance of VCC1 pass device during low drop operation for I = 100mA Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 64 TLE9262-3BQX Voltage Regulator 1 Figure 18 On-resistance range of VCC1 pass device during low drop operation for I = 150mA Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 65: Voltage Regulator 2

    TLE9262-3BQX Voltage Regulator 2 Voltage Regulator 2 Block Description V CC2 Vref Overtemperature State Shutdown Machine Bandgap Reference Figure 19 Module Block Diagram Functional Features • 5 V low-drop voltage regulator • Protected against short to battery voltage, e.g. for off-board sensor supply •...

  • Page 66: Functional Description

    TLE9262-3BQX Voltage Regulator 2 Functional Description In SBC Normal Mode VCC2 can be switched on or off via SPI. For SBC Stop- or Sleep Mode, the VCC2 has to be switched on or off before entering the respective SBC mode.

  • Page 67: Electrical Characteristics

    TLE9262-3BQX Voltage Regulator 2 Electrical Characteristics Table 17 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Values Parameter Symbol...
  • Page 68 TLE9262-3BQX Voltage Regulator 2 Figure 20 Typical on-resistance of VCC2 pass device during low drop operation for I = 30mA Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 69 TLE9262-3BQX Voltage Regulator 2 Figure 21 On-resistance range of VCC2 pass device during low drop operation for I = 50mA Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 70: External Voltage Regulator 3

    TLE9262-3BQX External Voltage Regulator 3 External Voltage Regulator 3 Block Description VCC3SH VCC3B VCC3REF CC3base CC3shunt > V shunt_threshold State Machine Figure 22 Functional Block Diagram Functional Features • Low-drop voltage regulator with external PNP transistor (up to 350mA with 470mΩ shunt resistor) •...

  • Page 71: Functional Description

    TLE9262-3BQX External Voltage Regulator 3 Functional Description The external voltage regulator can be used as an independent voltage regulator or in load-sharing mode with VCC1. Setting VCC3_ON in the M_S_CTRL register in SBC Normal Mode sets the stand-alone configuration of VCC3 as an independent voltage regulator.

  • Page 72: External Voltage Regulator As Independent Voltage Regulator

    TLE9262-3BQX External Voltage Regulator 3 when the bit VCC3_LS_ STP_ON is set and when load sharing is configured (for detailed protection features Chapter 15.7 Chapter 16.3). Table 19 External Voltage Regulator State by SBC Mode SBC Mode Load Sharing Mode...

  • Page 73: External Voltage Regulator In Load Sharing Mode

    TLE9262-3BQX External Voltage Regulator 3 SHUNT 100 Ω VCC3SH VCC3B VCC3REF CC3base CC3shunt > V shunt_threshold State Machine Figure 24 Protecting the VCC3 against inductive short circuits when configured as an independent voltage regulator for off-board supply 8.2.2 External Voltage Regulator in Load Sharing Mode The purpose of the load sharing mode is to increase the total current capability of VCC1 without increase of the power dissipation within the SBC.

  • Page 74: External Components

    Figure 25 VCC3 in Load Sharing Configuration External Components Characterization is performed with the BCP52-16 from Infineon (I < 200 mA) and with MJD253. Other PNP transistors can be used. However, the functionality must be checked in the application. Figure 25 shows one hardware set up used.

  • Page 75: Calculation Of R

    TLE9262-3BQX External Voltage Regulator 3 Calculation of R SHUNT As a independent regulator, the maximum current I where the limit starts and the bit I > I is set is CC3max CC3max determined by the shunt resistor R and the Output Current Shunt Voltage Threshold V...

  • Page 76: Electrical Characteristics

    TLE9262-3BQX External Voltage Regulator 3 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all outputs open; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
  • Page 77 TLE9262-3BQX External Voltage Regulator 3 Table 21 Electrical Characteristics (cont’d) Values Parameter Symbol Note or Test Condition Number Min. Typ. Max. External Regulator Output SBC Normal Mode; P_8.6.14 CC3,out2 Voltage stand-alone (VCC3 = 5.0V) configuration 10 mA < I < 300 mA;...
  • Page 78 TLE9262-3BQX External Voltage Regulator 3 4) At Tj > 125°C, the power transistor leakage could be increased, which has to be added to the quiescent current of the application independently if the regulator is turned on/off. To prevent an overvoltage condition at no load due to this increased leakage, an internal clamping structure will automatically turn on at typ.
  • Page 79 TLE9262-3BQX External Voltage Regulator 3 Timing diagram for regulator reaction time “current increase regulation reaction time” and “current decrease regulation reaction time” CCbase CC3base, 50% rlinc rldec Figure 26 Regulator Reaction Time Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com.
  • Page 80 TLE9262-3BQX External Voltage Regulator 3 Typical Load Sharing Characteristics using the BCP52-16 PNP transistor and a 1 Ω shunt resistor 0,35 Tj = 27°C 0,30 Tj = 150°C 0,25 Tj = -40°C 0,20 0,15 0,10 0,05 - Icc3 vs. Icc1 Load Sharing Ratio - Icc1 vs.

  • Page 81: High-Side Switch

    TLE9262-3BQX High-Side Switch High-Side Switch Block Description VSHS HS Gate Control Overcurrent Detection Open Load (On) Figure 29 High-Side Module Block Diagram Features • Dedicated supply pin VSHS for high-side outputs • Overvoltage and undervoltage switch off - configurable via SPI •...

  • Page 82: Over- And Undervoltage Switch Off

    TLE9262-3BQX High-Side Switch 9.2.1 Over- and Undervoltage Switch Off All HS drivers in on-state are switched off in case of overvoltage on VSHS ). If the voltage drops below SHS,OVD the overvoltage threshold the HS drivers are activated again. The feature can be disabled by setting the SPI bit HS_OV_SD_EN.

  • Page 83: Pwm And Timer Function

    TLE9262-3BQX High-Side Switch 9.2.5 PWM and Timer Function Two 8-bit PWM generators are dedicated to generate a PWM signal on the HS outputs, e.g. for brightness adjustment or compensation of supply voltage fluctuation. The PWM generators are mapped to the dedicated HS outputs, and the duty cycle can be independently configured with a 8bit resolution via SPI (PWM1_CTRL, PWM2_CTRL).

  • Page 84: Electrical Characteristics

    TLE9262-3BQX High-Side Switch Electrical Characteristics Table 22 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Values Parameter Symbol Unit...

  • Page 85: High Speed Can Transceiver

    TLE9262-3BQX High Speed CAN Transceiver High Speed CAN Transceiver 10.1 Block Description VCAN SPI Mode Control Driver CANH Output TXDCAN Stage Temp.- CANL timeout Protection To SPI diagnostic VCAN = 2.5V BIAS CC 1 RXDCAN Receiver Wake Receiver Figure 30 Functional Block Diagram 10.2...
  • Page 86 TLE9262-3BQX High Speed CAN Transceiver The different transceiver modes can be controlled via the SPI bits. Figure 31 shows the possible transceiver mode transitions when changing the SBC mode. SBC Mode CAN Transceiver Mode SBC Stop Mode Receive Only Wake Capable...

  • Page 87: Can Off Mode

    TLE9262-3BQX High Speed CAN Transceiver 3QX variants of this family also support the CAN FD tolerant mode. See also Chapter 5.4.7 for more detailed information on how to enable the CAN FD tolerant mode. 10.2.1 CAN OFF Mode The CAN OFF Mode is the default mode after power-up of the SBC. It is available in all SBC Modes and is intended to completely stop CAN activities or when CAN communication is not needed.

  • Page 88: Can Receive Only Mode

    TLE9262-3BQX High Speed CAN Transceiver 10.2.3 CAN Receive Only Mode In CAN Receive Only Mode (RXD only), the driver stage is de-activated but reception is still operational. This mode is accessible by an SPI command in Normal Mode and in Stop Mode. The bus biasing is set to VCAN/2.
  • Page 89 TLE9262-3BQX High Speed CAN Transceiver Entering low -power mode , when selective wake-up function is disabled Bus recessive > t or not supported WAKE1 Wait Bias off Bias off Bus dominant > t WAKE1 optional: expired WAKE2 Bias off Bus recessive > t...
  • Page 90 TLE9262-3BQX High Speed CAN Transceiver Wake-Up in SBC Stop and Normal Mode In SBC Stop Mode, if a wake-up is detected, it is always signaled by the INT output and in the WK_STAT_1 register. It is also signaled by RXDCAN pulled to low. The same applies for the SBC Normal Mode. The microcontroller should set the device from SBC Stop Mode to SBC Normal Mode, there is no automatic transition to Normal Mode.

  • Page 91: Txd Time-Out Feature

    TLE9262-3BQX High Speed CAN Transceiver 10.2.5 TXD Time-out Feature If the TXD signal is dominant for a time t > t , in CAN Normal Mode, the TXD time-out function TXD_CAN_TO deactivates the transmission of the signal at the bus. This is implemented to prevent the bus from being blocked permanently due to an error.

  • Page 92: Electrical Characteristics

    TLE9262-3BQX High Speed CAN Transceiver 10.3 Electrical Characteristics Table 24 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; 4.75 V < V < 5.25 V; R = 60Ω; CAN Normal Mode; all voltages with...
  • Page 93 TLE9262-3BQX High Speed CAN Transceiver Table 24 Electrical Characteristics (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; 4.75 V < V < 5.25 V; R = 60Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin...
  • Page 94 TLE9262-3BQX High Speed CAN Transceiver Table 24 Electrical Characteristics (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; 4.75 V < V < 5.25 V; R = 60Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin...
  • Page 95 TLE9262-3BQX High Speed CAN Transceiver Table 24 Electrical Characteristics (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; 4.75 V < V < 5.25 V; R = 60Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin...
  • Page 96 TLE9262-3BQX High Speed CAN Transceiver Table 24 Electrical Characteristics (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; 4.75 V < V < 5.25 V; R = 60Ω; CAN Normal Mode; all voltages with respect to ground, positive current flowing into pin...
  • Page 97 TLE9262-3BQX High Speed CAN Transceiver 1) Not subject to production test, specified by design. shall be observed during dominant and recessive state and also during the transition dominant to recessive and vice versa while TXD is simulated by a square signal (50% duty cycle) with a frequency of up to 1 MHz (2 MBit/s);...
  • Page 98 TLE9262-3BQX High Speed CAN Transceiver TXDCAN 5x t Bit(TXD) Bit(TXD) Loop_f =CANH-CANL diff 900mV 500mV Bit(Bus) RXDCAN Loop_r Bit(RXD) Figure 36 From ISO 11898-2: tloop, tbit(TXD), tbit(Bus), tbit(RXD) definitions Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 99: Lin Transceiver

    TLE9262-3BQX LIN Transceiver LIN Transceiver 11.1 Block Description VSHS SPI Mode Control VCC1 Driver TxD Input Temp.- Output Protection Current TXDLIN Stage Timeout Limit To SPI Diagnostic Receiver VCC1 Filter VSHS RXDLIN Wake Receiver Figure 37 Block Diagram 11.1.1 LIN Specifications The LIN network is standardized by international regulations.

  • Page 100: Functional Description

    TLE9262-3BQX are the interface between the micro controller and the physical LIN Bus. The digital output data from the micro controller are driven to the LIN bus via the TXD input pin on the TLE9262-3BQX. The transmit data stream on the TXD input is converted to a LIN bus signal with optimized slew rate to minimize the EME level of the LIN network.

  • Page 101: Lin Normal Mode

    TLE9262-3BQX LIN Transceiver 11.2.2 LIN Normal Mode The LIN Transceiver is enabled via SPI in SBC Normal Mode. LIN Normal Mode is designed for normal data transmission/reception within the LIN network. The Mode is available in SBC Normal Mode and in SBC Stop Mode.

  • Page 102: Lin Wake Capable Mode

    TLE9262-3BQX LIN Transceiver 11.2.4 LIN Wake Capable Mode This mode can be used in SBC Stop, Sleep, Restart and Normal Mode by programming via SPI and it is used to monitor bus activities. It is automatically accessed in SBC Fail-Safe Mode. A wake up is detected, if a recessive...

  • Page 103: Txd Time-Out Feature

    In case the supply voltage is dropping below the VSHS undervoltage detection threshold (VSHS < V ), the SHS,UVD TLE9262-3BQX disables the output and receiver stages. If the power supply reaches a higher level than the undervoltage detection threshold (VSHS > V ), the TLE9262-3BQX continues with normal operation. The SHS,UVD transceiver configuration stays unchanged.

  • Page 104: Slope Selection

    TLE9262-3BQX LIN Transceiver 11.2.8 Slope Selection The LIN transceiver offers a LIN Low-Slope Mode for 10.4 kBaud communication and a LIN Normal-Slope Mode for 20 kBaud communication. The only difference is the behavior of the transmitter. In LIN Low-Slope Mode, transmitter uses a lower slew rate to further reduce the EME compared to Normal-Slope Mode.

  • Page 105: Electrical Characteristics

    TLE9262-3BQX LIN Transceiver 11.3 Electrical Characteristics Table 26 Electrical Characteristics = 5.5 V to 18 V, T = -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified)
  • Page 106 TLE9262-3BQX LIN Transceiver Table 26 Electrical Characteristics (cont’d) = 5.5 V to 18 V, T = -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Values...
  • Page 107 TLE9262-3BQX LIN Transceiver Table 26 Electrical Characteristics (cont’d) = 5.5 V to 18 V, T = -40 °C to +150 °C, RL = 500 Ω, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Values...
  • Page 108 TLE9262-3BQX LIN Transceiver VSHS 100 nF Figure 41 Simplified Test Circuit for Dynamic Characteristics Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 109 TLE9262-3BQX LIN Transceiver (input to transmitting node ) Bus _dom (max ) Bus_rec (min ) Thresholds of Rec (max) receiving node 1 Dom (max) (Transceiver supply of transmitting Thresholds of node ) Rec(min ) receiving node 2 Dom(min ) Bus _dom (min )

  • Page 110: Wake And Voltage Monitoring Inputs

    TLE9262-3BQX Wake and Voltage Monitoring Inputs Wake and Voltage Monitoring Inputs 12.1 Block Description Internal Supply PU_WK PD_WK Logic MONx_Input_Circuit_ext.vsd Figure 43 Wake Input Block Diagram Features • Three High-Voltage inputs with a 3V (typ.) threshold voltage • Alternate Measurement function for high-voltage sensing via WK1 and WK2 •...

  • Page 111: Functional Description

    TLE9262-3BQX Wake and Voltage Monitoring Inputs 12.2 Functional Description The wake input pins are edge-sensitive inputs with a switching threshold of typically 3V. This means that both transitions, HIGH to LOW and LOW to HIGH, result in a signalization by the SBC. The signalization occurs either in triggering the interrupt in SBC Normal Mode and SBC Stop Mode or by a wake up of the device in SBC Sleep and SBC Fail-Safe Mode.

  • Page 112: Wake Input Configuration

    TLE9262-3BQX Wake and Voltage Monitoring Inputs 12.2.1 Wake Input Configuration To ensure a defined and stable voltage levels at the internal comparator input it is possible to configure integrated current sources via the SPI register WK_PUPD_CTRL. In addition, the wake detection modes (including the filter time) can be configured via the SPI register WK_FLT_CTRL.
  • Page 113 TLE9262-3BQX Wake and Voltage Monitoring Inputs Config C or D are intended for cyclic sense configuration. With the filter settings, the respective timer needs to be assigned to one or more HS output, which supplies an external circuit connected to the WKx pin, e.g. HS1...

  • Page 114: Alternate Measurement Function With Wk1 And Wk2

    TLE9262-3BQX Wake and Voltage Monitoring Inputs 12.2.2 Alternate Measurement Function with WK1 and WK2 12.2.2.1 Block Description This function provides the possibility to measure a voltage, e.g. the unbuffered battery voltage, with the protected WK1 HV-input. The measured voltage is routed out at WK2. It allows for example a voltage compensation for LED lighting by changing the duty cycle of the High-Side outputs.

  • Page 115: Electrical Characteristics

    TLE9262-3BQX Wake and Voltage Monitoring Inputs Note: There is a diode in series to the switch S1 (not shown in the Figure 65), which will influence the temperature behavior of the switch. 12.3 Electrical Characteristics Table 30 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C;...
  • Page 116 TLE9262-3BQX Wake and Voltage Monitoring Inputs 1100 VS = 13.5V 1000 500 μA 250 μA 100 μA 50 μA JUNCTION TEMPERATURE (°C) Figure 46 Typical Drop Voltage Characteristics of S1 (between WK1 & WK2) Data Sheet Rev. 1.00 2017-07-31 Arrow.com.

  • Page 117: Interrupt Function

    TLE9262-3BQX Interrupt Function Interrupt Function 13.1 Block and Functional Description Time Interrupt logic Figure 47 Interrupt Block Diagram The interrupt is used to signalize special events in real time to the microcontroller. The interrupt block is designed as a push/pull output stage as shown in Figure 47.
  • Page 118 TLE9262-3BQX Interrupt Function INTD Update of Update of WK_STAT register WK_STAT register optional Read & Clear WK_STAT no WK no WK contents No SPI Read & Clear Read & Clear Command sent WK_STAT WK1 + WK2 no WK contents Interrupt_Behavior .vsd...

  • Page 119: Electrical Characteristics

    TLE9262-3BQX Interrupt Function 13.2 Electrical Characteristics Table 31 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.

  • Page 120: Fail Outputs

    TLE9262-3BQX Fail Outputs Fail Outputs 14.1 Block and Functional Description 5V_int SBC Init Mode test TEST FO1/2 Failure logic FO3/TEST FO_PL Failure Logic Figure 49 Simplified Fail Output Block Diagram for FO1/2 and for FO3/TEST The fail outputs consist of a failure logic block and three open-drain outputs (FO1, FO2, FO3) with active-low signalization.

  • Page 121: General Purpose I/O Functionality Of Fo2 And Fo3 As Alternate Function

    TLE9262-3BQX Fail Outputs Note: The Fail output pin is triggered for any of the above described failures. No FAILURE is caused for the 1st watchdog failure if selected for Config2. The three fail outputs are activated simultaneously with following output functionalities: FO1: Static fail output •...
  • Page 122 TLE9262-3BQX Fail Outputs Table 32 Fail-Output and GPIO configuration behavior during the respective SBC Modes SBC Normal SBC Stop Mode SBC Sleep Mode SBC Restart SBC Fail-Safe Configuration Mode Mode Mode FOx (default) fixed fixed active / fixed active configurable...

  • Page 123: Electrical Characteristics

    TLE9262-3BQX Fail Outputs 14.2 Electrical Characteristics Table 33 Electrical Characteristics = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
  • Page 124 TLE9262-3BQX Fail Outputs 1) The FOx drivers are supplied via VS. However, the GPIO HS switches (FO2, FO3/TEST) are supplied by VSHS 2) The external capacitance on this pin must be limited to less than 10nF to ensure proper detection of SBC Development Mode and SBC User Mode operation.

  • Page 125: Supervision Functions

    TLE9262-3BQX Supervision Functions Supervision Functions 15.1 Reset Function Reset logic Incl. filter & delay Figure 51 Reset Block Diagram 15.1.1 Reset Output Description The reset output pin RO provides a reset information to the microcontroller, for example, in the event that the output voltage has fallen below the undervoltage threshold V .

  • Page 126: Soft Reset Description

    TLE9262-3BQX Supervision Functions t < t The reset threshold can be configured via SPI in SBC Normal Mode , default is V undervoltage Init Trigger Trigger Init = long open window = closed window = open window SBC Init SBC Normal...

  • Page 127: Watchdog Function

    TLE9262-3BQX Supervision Functions 15.2 Watchdog Function The watchdog is used to monitor the software execution of the microcontroller and to trigger a reset if the microcontroller stops serving the watchdog due to a lock up in the software. Two different types of watchdog functions are implemented and can be selected via the bit WD_WIN: •...

  • Page 128: Time-Out Watchdog

    TLE9262-3BQX Supervision Functions Depending on the configuration, the WD_FAIL bits will be set after a watchdog trigger failure as follows: • In case an incorrect WD trigger is received (triggering in the closed watchdog window or when the watchdog WD_FAIL...

  • Page 129: Window Watchdog

    TLE9262-3BQX Supervision Functions 15.2.2 Window Watchdog Compared to the time-out watchdog the characteristic of the window watchdog is that the watchdog timer period is divided between an closed and an open window. The watchdog must be triggered within the open window.

  • Page 130: Watchdog Setting Check Sum

    TLE9262-3BQX Supervision Functions 15.2.3 Watchdog Setting Check Sum A check sum bit is part of the SPI commend to trigger the watchdog and to set the watchdog setting. The sum of the 8 data bits in the register WWD_CTRL needs to have even parity (see Equation (15.1)).

  • Page 131: Watchdog During Sbc Stop Mode

    TLE9262-3BQX Supervision Functions 15.2.4 Watchdog during SBC Stop Mode The watchdog can be disabled for SBC Stop Mode in SBC Normal Mode. For safety reasons, there is a special sequence to be followed in order to disable the watchdog as described in Figure 55.

  • Page 132: Watchdog Start In Sbc Stop Mode Due To Bus Wake

    TLE9262-3BQX Supervision Functions 15.2.5 Watchdog Start in SBC Stop Mode due to Bus Wake In SBC Stop Mode the Watchdog can be disabled. In addition a feature is available which will start the watchdog with any BUS wake (CAN or LIN) during SBC Stop Mode. The feature is enabled by setting the bit WD_EN_ WK_BUS (= default value after POR).

  • Page 133: Vs Power On Reset

    TLE9262-3BQX Supervision Functions 15.3 VS Power On Reset At power up of the device, the VS Power on Reset is detected when VS > and the SPI bit is set to POR,r indicate that all SPI registers are set to POR default settings. VCC1 is starting up and the reset output will be...

  • Page 134: Undervoltage Vs And Vshs

    TLE9262-3BQX Supervision Functions 15.4 Undervoltage VS and VSHS If the supply voltage VS reaches the undervoltage threshold then the SBC does the following measures: S,UV VS_UV • SPI bit is set. No other error bits are set. The bit can be cleared once the condition is not present anymore, Chapter 8.2...

  • Page 135: Vcc1 Overvoltage

    TLE9262-3BQX Supervision Functions VCC1 SBC Normal SBC Restart SBC Normal Figure 57 VCC1 Undervoltage Timing Diagram An additional safety mechanism is implemented to avoid repetitive VCC1 undervoltage resets due to high dynamic loads on VCC1: • A counter is increased for every consecutive VCC1 undervoltage event (regardless on the selected reset threshold), •...

  • Page 136: Vcc1 Short Circuit And Vcc3 Diagnostics

    TLE9262-3BQX Supervision Functions that external noise could be coupled into the VCC1 supply line. Especially, in case the VCC1 output current in SBC STOP Mode is below the active peak threshold (I VCC1,Ipeak VCC1 CC1,OV VCC1,OV_F SBC Normal SBC Restart...

  • Page 137: Thermal Protection

    TLE9262-3BQX Supervision Functions 15.9 Thermal Protection Three independent and different thermal protection features are implemented in the SBC according to the system impact: • Individual thermal shutdown of specific blocks • Temperature prewarning of main microcontroller supply VCC1 • SBC thermal shutdown due to VCC1 overtemperature 15.9.1...

  • Page 138: Temperature Prewarning

    TLE9262-3BQX Supervision Functions 15.9.2 Temperature Prewarning As a next level of thermal protection a temperature prewarning is implemented if the main supply VCC1 reaches the thermal prewarning temperature threshold . Then the status bit is set. This bit can only be cleared via SPI once the overtemperature is not present anymore.

  • Page 139: Electrical Characteristics

    TLE9262-3BQX Supervision Functions 15.10 Electrical Characteristics Table 35 Electrical Specification = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
  • Page 140 TLE9262-3BQX Supervision Functions Table 35 Electrical Specification (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Values...
  • Page 141 TLE9262-3BQX Supervision Functions Table 35 Electrical Specification (cont’d) = 5.5 V to 28 V; T = -40 °C to +150 °C; SBC Normal Mode; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Values...

  • Page 142: Serial Peripheral Interface

    TLE9262-3BQX Serial Peripheral Interface Serial Peripheral Interface 16.1 SPI Block Description The 16-bit wide Control Input Word is read via the data input SDI, which is synchronized with the clock input CLK provided by the microcontroller. The output word appears synchronously at the data output SDO (see Figure 59).

  • Page 143: Failure Signalization In The Spi Data Output

    TLE9262-3BQX Serial Peripheral Interface 16.2 Failure Signalization in the SPI Data Output When the microcontroller sends a wrong SPI command to the SBC, the SBC ignores the information. Wrong SPI commands are either invalid SBC mode commands or commands which are prohibited by the state machine to avoid undesired device or system states (see below).
  • Page 144 TLE9262-3BQX Serial Peripheral Interface Note: In order to read the SPI ERR flag properly, CLK must be low when CSN is triggered, i.e. the ERR bit is not valid if the CLK is high on a falling edge of CSN...

  • Page 145: Spi Programming

    SPI Programming For the TLE9262-3BQX, 7 bits are used or the address selection (BIT6...0). Bit 7 is used to decide between Read Only and Read & Clear for the status bits, and between Write and Read Only for configuration bits. For the actual configuration and status information, 8 data bits (BIT15...8) are used.
  • Page 146 TLE9262-3BQX Serial Peripheral Interface 10 11 12 13 Address Bits Data Bits Register content of selected address 10 11 12 13 Status Information Field Data Bits time LSB is sent first in SPI message Figure 60 SPI Operation Mode Data Sheet Rev.

  • Page 147: Spi Bit Mapping

    TLE9262-3BQX Serial Peripheral Interface 16.4 SPI Bit Mapping The following figures show the mapping of the registers and the SPI bits of the respective registers. The Control Registers ‘000 0000’ to ‘001 1110’ are Read/Write Register. Depending on bit 7 the bits are only read (setting bit 7 to ‘0’) or also written (setting bit 7 to ‘1’).
  • Page 148 TLE9262-3BQX Serial Peripheral Interface 15 14 13 12 11 10 8 Data Bits [bits 8...15] 7 Address Bits [bits 0...6] Reg. Type for Configuration & Status Information for Register Selection M_S_CTRL 0 0 0 0 0 0 1 HW_CTRL 0 0 0...
  • Page 149 R E G I S T E R S FAM_PROD_STAT FAM_3 FAM_2 FAM_1 FAM_0 PROD_3 PROD_2 PROD_1 PROD_0 read 1111110 Figure 62 TLE9262-3BQX SPI Bit Mapping including Selective Wake Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 150: Spi Control Registers

    TLE9262-3BQX Serial Peripheral Interface 16.5 SPI Control Registers READ/WRITE Operation (see also Chapter 16.3): • The ‘POR / Soft Reset Value’ defines the register content after POR or SBC Reset. • The ‘Restart Value’ defines the register content after SBC Restart, where ‘x’ means the bit is unchanged.

  • Page 151: General Control Registers

    TLE9262-3BQX Serial Peripheral Interface 16.5.1 General Control Registers M_S_CTRL Mode- and Supply Control (Address 000 0001 POR / Soft Reset Value: 0000 0000 Restart Value: 00x0 00xx VCC1_OV_RS MODE_1 MODE_0 VCC3_ON VCC2_ON_1 VCC2_ON_0 VCC1_RT_1 VCC1_RT_0 Field Bits Type Description MODE...
  • Page 152 TLE9262-3BQX Serial Peripheral Interface HW_CTRL Mode- and Supply Control (Address 000 0010 POR / Soft Reset Value: y000 y000 Restart Value: xx0x x00x SOFT_RESET VCC3_VS_UV VCC3_LS_ST VCC3_V_CFG FO_ON VCC3_LS Reserved _OFF P_ON Field Bits Type Description VCC3_ VCC3 Output Voltage Configuration (if configured as...
  • Page 153 TLE9262-3BQX Serial Peripheral Interface If the FO_ON bit is set by the software then it will be cleared by the SBC after SBC Restart Mode was entered and the FOx outputs will be disabled. See also Chapter 14 for FOx activation and deactivation.
  • Page 154 TLE9262-3BQX Serial Peripheral Interface WD_CTRL Watchdog Control (Address 000 0011 POR / Soft Reset Value: 0001 0100 Restart Value: x0xx 0100 WD_STM_ WD_EN_ CHECKSUM WD_WIN Reserved WD_TIMER_2 WD_TIMER_1 WD_TIMER_0 EN_0 WK_BUS Field Bits Type Description CHECKSUM 7 Watchdog Setting Check Sum Bit...
  • Page 155 TLE9262-3BQX Serial Peripheral Interface BUS_CTRL_1 Bus Control (Address 000 0100 POR / Soft Reset Value: 0010 0000 ; Restart Value: xxxy yyyy LIN_FLASH LIN_LSM LIN_TXD_TO LIN1_1 LIN1_0 CAN_2 CAN_1 CAN_0 Field Bits Type Description LIN_FLASH LIN Flash Programming Mode , Slope control mechanism active...
  • Page 156 TLE9262-3BQX Serial Peripheral Interface capable or OFF then the mode will remain unchanged.The Receive Only Mode has to be selected by the user before entering SBC Stop Mode. Please refer to Chapter 5.4.4 for detailed information on the Selective Wake mode changes.
  • Page 157 TLE9262-3BQX Serial Peripheral Interface WK_CTRL_1 Internal Wake Input Control (Address 000 0110 POR / Soft Reset Value: 0000 0000 Restart Value: xx00 0000 TIMER2_WK_ TIMER1_WK_ WD_STM_ Reserved Reserved Reserved Reserved Reserved EN_1 Field Bits Type Description TIMER2_WK Timer2 Wake Source Control (for cyclic wake)
  • Page 158 TLE9262-3BQX Serial Peripheral Interface WK_CTRL_2 External Wake Source Control (Address 000 0111 POR / Soft Reset Value: 0000 0111 Restart Value: x0x0 0xxx INT_GLOBAL Reserved WK_MEAS Reserved Reserved WK3_EN WK2_EN WK1_EN Field Bits Type Description INT_ Global Interrupt Configuration (see also Chapter 13.1)
  • Page 159 TLE9262-3BQX Serial Peripheral Interface WK_PUPD_CTRL Wake Input Level Control (Address 000 1000 POR / Soft Reset Value: 0000 0000 Restart Value: 00xx xxxx Reserved Reserved WK3_PUPD_1 WK3_PUPD_0 WK2_PUPD_1 WK2_PUPD_0 WK1_PUPD_1 WK1_PUPD_0 Field Bits Type Description Reserved Reserved, always reads as 0...
  • Page 160 TLE9262-3BQX Serial Peripheral Interface WK_FLT_CTRL Wake Input Filter Time Control (Address 000 1001 POR / Soft Reset Value: 0000 0000 Restart Value: 00xx xxxx Reserved Reserved WK3_FLT_1 WK3_FLT_0 WK2_FLT_1 WK2_FLT_0 WK1_FLT_1 WK1_FLT_0 Field Bits Type Description Reserved Reserved, always reads as 0...
  • Page 161 TLE9262-3BQX Serial Peripheral Interface TIMER1_CTRL Timer1 Control and Selection (Address 000 1100 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0000 TIMER1_ TIMER1_ TIMER1_ TIMER1_ TIMER1_ TIMER1_ Reserved Reserved ON_2 ON_1 ON_0 PER_2 PER_1 PER_0 Field Bits Type...
  • Page 162 TLE9262-3BQX Serial Peripheral Interface TIMER2_CTRL Timer2 Control and selection (Address 000 1101 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0000 TIMER2_ TIMER2_ TIMER2_ TIMER2_ TIMER2_ TIMER2_ Reserved Reserved ON_2 ON_1 ON_0 PER_2 PER_1 PER_0 Field Bits Type...
  • Page 163 TLE9262-3BQX Serial Peripheral Interface SW_SD_CTRL Switch Shutdown Control (Address 001 0000 POR / Soft Reset Value: 0000 0000 Restart Value: 0xxx 0000 HS_OV_SD_E HS_UV_SD_E HS_OV_UV_R Reserved Reserved Reserved Reserved Reserved Field Bits Type Description Reserved Reserved, always reads as 0 HS_OV_SD_ Shutdown Disabling of HS1...4 in case of VSHS OV...
  • Page 164 TLE9262-3BQX Serial Peripheral Interface HS_CTRL1 High-Side Switch Control 1 (Address 001 0100 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0000 Reserved HS2_2 HS2_1 HS2_0 Reserved HS1_2 HS1_1 HS1_0 Field Bits Type Description Reserved Reserved, always reads as 0...
  • Page 165 TLE9262-3BQX Serial Peripheral Interface HS_CTRL2 High-Side Switch Control 2 (Address 001 0101 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0000 Reserved HS4_2 HS4_1 HS4_0 Reserved HS3_2 HS3_1 HS3_0 Field Bits Type Description Reserved Reserved, always reads as 0...
  • Page 166 TLE9262-3BQX Serial Peripheral Interface GPIO_CTRL GPIO Configuration Control (Address 001 0111 POR / Soft Reset Value: 0000 0000 Restart Value: xxxx xxxx FO_DC_1 FO_DC_0 GPIO2_2 GPIO2_1 GPIO2_0 GPIO1_2 GPIO1_1 GPIO1_0 Field Bits Type Description FO_DC Duty Cycle Configuration of FO3 (if selected)
  • Page 167 TLE9262-3BQX Serial Peripheral Interface PWM1_CTRL PWM1 Configuration Control (Address 001 1000 POR / Soft Reset Value: 0000 0000 Restart Value: xxxx xxxx PWM1_DC_7 PWM1_DC_6 PWM1_DC_5 PWM1_DC_4 PWM1_DC_3 PWM1_DC_2 PWM1_DC_1 PWM1_DC_0 Field Bits Type Description PWM1_DC PWM1 Duty Cycle (bit0=LSB; bit7=MSB)
  • Page 168 TLE9262-3BQX Serial Peripheral Interface PWM_FREQ_CTRL PWM Frequency Configuration Control (Address 001 1100 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0x0x Reserved Reserved Reserved Reserved Reserved PWM2_FREQ Reserved PWM1_FREQ Field Bits Type Description Reserved Reserved, always reads as 0...

  • Page 169: Selective Wake Control Registers

    TLE9262-3BQX Serial Peripheral Interface 16.5.2 Selective Wake Control Registers SWK_CTRL CAN Selective Wake Control (Address 010 0000 POR / Soft Reset Value: 0000 0000 Restart Value: xxxx 0000 CANTO_ OSC_CAL TRIM_EN_1 TRIM_EN_0 Reserved Reserved Reserved CFG_VAL MASK Field Bits Type...
  • Page 170 TLE9262-3BQX Serial Peripheral Interface SWK_BTL1_CTRL SWK Bit Timing Logic Control1 (Address 010 0001 POR / Soft Reset Value: 1010 0000 Restart Value: xxxx xxxx TBIT_7 TBIT_6 TBIT_5 TBIT_4 TBIT_3 TBIT_2 TBIT_1 TBIT_0 Field Bits Type Description TBIT Number of Time Quanta in a Bit Time Represents the number of time quanta in a bit time.
  • Page 171 TLE9262-3BQX Serial Peripheral Interface SWK_ID2_CTRL SWK WUF Identifier bits 20...13 (Address 010 0100 POR / Soft Reset Value: 0000 0000 ; Restart Value: xxxx xxxx ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 Field Bits Type Description ID20_13 WUF Identifier Bits 20...13 SWK_ID1_CTRL SWK WUF Identifier bits 12...5 (Address 010 0101...
  • Page 172 TLE9262-3BQX Serial Peripheral Interface Note: The setting RTR = 1 is not allowed for wake-up frames according to the ISO11898-2:2016 Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 173 TLE9262-3BQX Serial Peripheral Interface SWK_MASK_ID3_CTRL SWK WUF Identifier Mask bits 28...21 (Address 010 0111 POR / Soft Reset Value: 0000 0000 ; Restart Value: xxxx xxxx MASK_ID28 MASK_ID27 MASK_ID26 MASK_ID25 MASK_ID24 MASK_ID23 MASK_ID22 MASK_ID21 Field Bits Type Description MASK_ID28 WUF Identifier Mask Bits 28...21...
  • Page 174 TLE9262-3BQX Serial Peripheral Interface SWK_MASK_ID1_CTRL SWK WUF Identifier Mask bits 12...5 (Address 010 1001 POR / Soft Reset Value: 0000 0000 ; Restart Value: xxxx xxxx MASK_ID12 MASK_ID11 MASK_ID10 MASK_ID9 MASK_ID8 MASK_ID7 MASK_ID6 MASK_ID5 Field Bits Type Description MASK_ID12 WUF Identifier Mask Bits 12...5...
  • Page 175 TLE9262-3BQX Serial Peripheral Interface SWK_DLC_CTRL SWK Frame Data Length Code Control (Address 010 1011 POR / Soft Reset Value: 0000 0000 ; Restart Value: 0000 xxxx Reserved Reserved Reserved Reserved DLC_3 DLC_2 DLC_1 DLC_0 Field Bits Type Description Reserved Reserved, always reads as 0...
  • Page 176 TLE9262-3BQX Serial Peripheral Interface SWK_DATA6_CTRL SWK Data6 Register (Address 010 1101 POR / Soft Reset Value: 0000 0000 ; Restart Value: xxxx xxxx DATA6_7 DATA6_6 DATA6_5 DATA6_4 DATA6_3 DATA6_2 DATA6_1 DATA6_0 Field Bits Type Description DATA6 Data6 byte content (bit0=LSB; bit7=MSB)
  • Page 177 TLE9262-3BQX Serial Peripheral Interface Field Bits Type Description DATA3 Data3 byte content (bit0=LSB; bit7=MSB) Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 178 TLE9262-3BQX Serial Peripheral Interface SWK_DATA2_CTRL SWK Data2 Register (Address 011 0001 POR / Soft Reset Value: 0000 0000 ; Restart Value: xxxx xxxx DATA2_7 DATA2_6 DATA2_5 DATA2_4 DATA2_3 DATA2_2 DATA2_1 DATA2_0 Field Bits Type Description DATA2 Data2 byte content (bit0=LSB; bit7=MSB)
  • Page 179 TLE9262-3BQX Serial Peripheral Interface Field Bits Type Description Reserved Reserved, always reads as 0 DIS_ERR_ Error Counter Disable Function , Error Counter is enabled during SWK , Error counter is disabled during SWK only if CAN_FD_EN = ‘1’ RX_FILT_ RX Receiver Filter Bypass...

  • Page 180: Selective Wake Trimming And Calibration Control Registers

    TLE9262-3BQX Serial Peripheral Interface 16.5.3 Selective Wake Trimming and Calibration Control Registers SWK_OSC_TRIM_CTRL SWK Oscillator Trimming Register (Address 011 1000 POR / Soft Reset Value: xxxx xxxx ; Restart Value: xxxx xxxx TRIM_OSC_7 TRIM_OSC_6 TRIM_OSC_5 TRIM_OSC_4 TRIM_OSC_3 TRIM_OSC_2 TRIM_OSC_1 TRIM_OSC_0...
  • Page 181 TLE9262-3BQX Serial Peripheral Interface Note: TRIM_OSC[8:12] represent the 32-steps coarse trimming range, which is not monotonous. It is not recommended to change these values. SWK_OSC_CAL_H_STAT SWK Oscillator Calibration High Register (Address 011 1010 POR / Soft Reset Value: 0000 0000 ;...
  • Page 182 TLE9262-3BQX Serial Peripheral Interface SWK_CDR_CTRL1 CDR Control 1 Register (Address 011 1100 POR / Soft Reset Value: 0000 0100 ; Restart Value: 0000 xx0x Reserved Reserved Reserved Reserved SEL_FILT_1 SEL_FILT_0 Reserved CDR_EN Field Bits Type Description Reserved Reserved, always reads as 0...
  • Page 183 TLE9262-3BQX Serial Peripheral Interface Table 37 Frequency Settings of Internal Clock for the CDR (cont’d) SEL_OSC_CLK[1:0] int. Clock for CDR 20 MHz 10 MHz Table 38 Recommended CDR Settings for Different Baud Rates SEL_OSC_CLK Baudrate SWK_BTL1_CTRL Value SWK_CDR_LIMIT_HIGH SWK_CDR_LIMIT_LOW_ [1:0]...
  • Page 184 TLE9262-3BQX Serial Peripheral Interface Field Bits Type Description CDR_LIM_L 7:0 Lower Bit Time Detection Range of Clock and Data Recovery SWK_BTL1_CTRL values < - 5% will be clamped Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 185: Spi Status Information Registers

    TLE9262-3BQX Serial Peripheral Interface 16.6 SPI Status Information Registers READ/CLEAR Operation (see also Chapter 16.3): • One 16-bit SPI command consist of two bytes: - the 7-bit address and one additional bit for the register access mode and - following the data byte The numbering of following bit definitions refers to the data byte and correspond to the bits D0...D7 and to...

  • Page 186: General Status Registers

    TLE9262-3BQX Serial Peripheral Interface 16.6.1 General Status Registers SUP_STAT_2 Supply Voltage Fail Status (Address 100 0000 POR / Soft Reset Value: 0000 0000 Restart Value: 0x0x xxxx Reserved VS_UV Reserved VCC3_OC VCC3_UV VCC3_OT VCC1_OV VCC1_WARN Field Bits Type Description Reserved...
  • Page 187 TLE9262-3BQX Serial Peripheral Interface SUP_STAT_1 Supply Voltage Fail Status (Address 100 0001 POR / Soft Reset Value: y000 0000 Restart Value: xxxx xx0x VSHS_UV VSHS_OV VCC2_OT VCC2_UV VCC1_SC VCC1_UV_FS VCC1_UV Field Bits Type Description Power-On Reset Detection , No POR...
  • Page 188 TLE9262-3BQX Serial Peripheral Interface THERM_STAT Thermal Protection Status (Address 100 0010 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 0xxx Reserved Reserved Reserved Reserved Reserved TSD2 TSD1 Field Bits Type Description Reserved Reserved, always reads as 0 TSD2...
  • Page 189 TLE9262-3BQX Serial Peripheral Interface DEV_STAT Device Information Status (Address 100 0011 POR / Soft Reset Value: 0000 0000 Restart Value: xx00 xxxx DEV_STAT_1 DEV_STAT_0 Reserved Reserved WD_FAIL_1 WD_FAIL_0 SPI_FAIL FAILURE Field Bits Type Description DEV_STAT Device Status before Restart Mode 00B , Cleared (Register must be actively cleared) 01B , Restart due to failure (WD fail, TSD2, VCC1_UV);...
  • Page 190 TLE9262-3BQX Serial Peripheral Interface BUS_STAT_1 Bus Communication Status (Address 100 0100 POR / Soft Reset Value: 0000 0000 Restart Value: 0xxx xxxx Reserved LIN1_FAIL_1 LIN1_FAIL_0 CANTO SYSERR CAN_FAIL_1 CAN_FAIL_0 VCAN_UV Field Bits Type Description Reserved Reserved, always reads as 0...
  • Page 191 TLE9262-3BQX Serial Peripheral Interface 3. CANTO will be set only if CAN2 = 1 (=SWK Mode enabled). It will be set as soon as CANSIL was set and will stay set even in CANSIL it is reset. An interrupt is issued in SBC Stop- and SBC Normal Mode as soon as CANTO is set and the interrupt is not masked out, i.e.
  • Page 192 TLE9262-3BQX Serial Peripheral Interface WK_STAT_1 Wake-up Source and Information Status (Address 100 0110 POR / Soft Reset Value: 0000 0000 Restart Value: 0xxx 0xxx Reserved LIN1_WU CAN_WU TIMER_WU Reserved WK3_WU WK2_WU WK1_WU Field Bits Type Description Reserved Reserved, always reads as 0...
  • Page 193 TLE9262-3BQX Serial Peripheral Interface WK_STAT_2 Wake-up Source and Information Status (Address 100 0111 POR / Soft Reset Value: 0000 0000 Restart Value: 00xx 0000 Reserved Reserved GPIO2_WU GPIO1_WU Reserved Reserved Reserved Reserved Field Bits Type Description Reserved Reserved, always reads as 0...
  • Page 194 TLE9262-3BQX Serial Peripheral Interface WK_LVL_STAT WK Input Level (Address 100 1000 POR / Soft Reset Value: xx00 0xxx Restart Value: xxxx 0xxx SBC_DEV CFGP GPIO2_LVL GPIO1_LVL Reserved WK3_LVL WK2_LVL WK1_LVL _LVL Field Bits Type Description SBC_DEV Status of SBC Operating Mode at FO3/TEST Pin...
  • Page 195 TLE9262-3BQX Serial Peripheral Interface HS_OC_OT_STAT High-Side Switch Overload Status (Address 101 0100 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 xxxx Reserved Reserved Reserved Reserved HS4_OC_OT HS3_OC_OT HS2_OC_OT HS1_OC_OT Field Bits Type Description Reserved Reserved, always reads as 0 HS4_OC_OT 3 Overcurrent &...
  • Page 196 TLE9262-3BQX Serial Peripheral Interface HS_OL_STAT High-Side Switch Open-Load Status (Address 101 0101 POR / Soft Reset Value: 0000 0000 Restart Value: 0000 xxxx Reserved Reserved Reserved Reserved HS4_OL HS3_OL HS2_OL HS1_OL Field Bits Type Description Reserved Reserved, always reads as 0...

  • Page 197: Selective Wake Status Registers

    TLE9262-3BQX Serial Peripheral Interface 16.6.2 Selective Wake Status Registers SWK_STAT Selective Wake Status (Address 111 0000 POR / Soft Reset Value: 0000 0000 Restart Value: 0x00 xxxx Reserved SYNC Reserved Reserved CANSIL SWK_SET Field Bits Type Description Reserved Reserved, always reads as 0...
  • Page 198 TLE9262-3BQX Serial Peripheral Interface SWK_ECNT_STAT SWK Status (Address 111 0001 POR / Soft Reset Value: 0000 0000 ; Restart Value: 00xx xxxx Reserved Reserved ECNT_5 ECNT_4 ECNT_3 ECNT_2 ECNT_1 ECNT_0 Field Bits Type Description Reserved Reserved, always reads as 0...
  • Page 199 TLE9262-3BQX Serial Peripheral Interface SWK_CDR_STAT1 CDR Status 1 Register (Address 111 0010 POR / Soft Reset Value: 1010 0000 ; Restart Value: xxxx xxxx N_AVG_11 N_AVG_10 N_AVG_9 N_AVG_8 N_AVG_7 N_AVG_6 N_AVG_5 N_AVG_4 Field Bits Type Description NAVG_SAT Output Value from Filter Block N_AVG is representing the integer part of the number of selected input clock frequency per CAN bus bit.

  • Page 200: Family And Product Information Register

    TLE9262-3BQX Serial Peripheral Interface 16.6.3 Family and Product Information Register FAM_PROD_STAT Family and Product Identification Register (Address 111 1110 POR / Soft Reset Value: 0011 yyyy Restart Value: 0011 yyyy FAM_3 FAM_2 FAM_1 FAM_0 PROD_3 PROD_2 PROD_1 PROD_0 Field Bits...

  • Page 201: Electrical Characteristics

    TLE9262-3BQX Serial Peripheral Interface 16.7 Electrical Characteristics Table 39 Electrical Characteristics = 5.5 V to 28 V, T = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol...
  • Page 202 TLE9262-3BQX Serial Peripheral Interface Table 39 Electrical Characteristics (cont’d) = 5.5 V to 28 V, T = -40 °C to +150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit...

  • Page 203: Application Information

    TLE9262-3BQX Application Information Application Information 17.1 Application Diagram Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device.
  • Page 204 TLE9262-3BQX Application Information Note: Unused outputs are recommended to be left unconnected on the application board. If unused output pins are routed to an external connector which leaves the ECU, then these pins should have provision for a zero ohm jumper (depopulated if unused) or ESD protection.
  • Page 205 Active Components e.g. BAS 3010A, Infineon Reverse polarity protection for VS supply pins e.g. BAS 3010A, Infineon Reverse polarity protection for VSHS supply pin; if separate supplies are not needed, then connect VSHS to VS pins As required by application, configure series resistor accordingly As required by application, configure series resistor accordingly e.g.
  • Page 206 TLE9262-3BQX Application Information VBAT VBAT e.g. 470uF VCC1 µC TxD LIN1 TxD LIN1 RxD LIN1 RxD LIN1 LOGIC State Machine TxD CAN TxD CAN RxD CAN RxD CAN Reset TLE9262 Vbat_uC ADC_x max. 500uA ≥10k ISO Pulse ≥10n protection Note: Vbat_uC Max.
  • Page 207 TLE9262-3BQX Application Information 5V_int SBC Init Mode test TEST Connector FO3/ /Jumper TEST FO_PL Failure Logic Figure 66 Hint for Increasing the Robustness of pin FO3/TEST during Debugging or Programming Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.

  • Page 208: Esd Tests

    TLE9262-3BQX Application Information 17.2 ESD Tests Note: Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) has been performed. The results and test conditions are available in a test report. The target values for the test are listed Table 41 below.

  • Page 209: Thermal Behavior Of Package

    TLE9262-3BQX Application Information 17.3 Thermal Behavior of Package Below figure shows the thermal resistance (R ) of the device vs. the cooling area on the bottom of the PCB th_JA for Ta = 85°C. Every line reflects a different PCB and thermal via design.
  • Page 210 TLE9262-3BQX Application Information Cross Section (JEDEC 2s2p) with Cooling Area Cross Section (JEDEC 1s0p) with Cooling Area 70µm modelled (traces) 35µm, 90% metalization* 35µm, 90% metalization* 70µm / 5% metalization + cooling area *: means percentual Cu metalization on each layer...

  • Page 211: Package Outlines

    The tie bars have an internal connection to the exposed pad. For assembly recommendations please also refer to the documents "Recommendations for Board Assembly (VQFN and IQFN)" and "VQFN48 Layout Hints" on the Infineon website (www.infineon.com). The PG-VQFN-48-31 package is a leadless exposed pad power package featuring Lead Tip Inspection (LTI) to support Automatic Optical Inspection (AOI).

  • Page 212: Revision History

    TLE9262-3BQX Revision History Revision History Revision Date Changes Rev. 1.00 2017-07-31 Initial Release Data Sheet Rev. 1.00 2017-07-31 Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com. Arrow.com.
  • Page 213 Infineon Technologies, customer's products and any use of the product of Infineon Technologies’ products may not be used in Infineon Technologies in customer's applications. any applications where a failure of the product or any...

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