ZiLOG Z8 Encore! XP F08 A Series User Manual page 21

R7 R7
D2 D2
PA6_nT1OUT
1 2
GREEN GREEN 100 100
R8 R8
D3 D3
PA7_T1OUT
1 2
100 100
YELL YELL
R10 R10
D4 D4
PC3_COUT
1 2
10 10
RED RED
VCC_33V
VCC_33V
GND
GND
PA0_T0IN_JP
PA1_T0OUT_JP
20 pin footprint
R20 R20 R21 R21
U6 U6
PB1_ANA1
1
PB1/ANA1
PB2_ANA2
2
PB2/ANA2
0 0 0 0 PB3_ANA3
3
PB3/CLKIN/ANA3
VCC_33V
4
VDD PC1ANA5/CINN/LED
PA0_T0IN
5
PA0/T0IN/T0OUT/XIN/ PC0/ANA4/CINP/LED
PA1_T0OUT
6
PA1/T0OUT/XOUT
GND
7
GND
PA2
8
PA2/DE
PA3_CTS0
9
PA3/CTS0
PA4_RXD0
10
PA4/RXD0
Z8F04xA Z8F04xA
R14 R14 R15 R15
0 0 0 0
R18 R18
1M 1M
Y1 Y1
1 3
1 3
C19 C19 C20 C20
20 MHz 20 MHz
NOTE 2
TABLE 2
Clock Mode R14 R15 R18 C19
Internal Only none none none none
Crystal 0 Ohm 220 Ohm none Yes
Ceramic Res 0 Ohm 0 Ohm none none
External CMOS none none none none
(Use PA0_T0IN
pin on JP2)
Schematic, Z8 Encore! XP
UM018603-1005
R9 R9
SW2 SW2
VCC_33V GND
TEST
100K 100K
R11 R11
100 100
PA2
NOTE 1:
R12 R12
0 0
U8 U8
VCC_33V
1 3
IO IO
EMI Filter EMI Filter
SENSE
PB0_ANA0
20
PB0/ANA0
PC3_COUT
19
PC3/COUT/LED
PC2_ANA6
18
PC2/ANA6/LED
PC1_ANA5 C23 C23 C22 C22
17
PC0_ANA4 + +
16
DBG 0.033uF C21 0.033uF C21 C10 C10
15
DBG
PD0 30uF 30uF
14
RESET/PD0
PA7_T1OUT 0.033uF 0.033uF 0.001uF 0.001uF
13
PA7/T1OUT
PA6_nT1OUT
12
PA6/T1IN/T1OUT
PA5_TXD0
11
PA5/TXD0
PA3_CTS0
PA4_RXD0
PA5_TXD0
R16 0 R16 0 R17 0 R17 0
GND
NOTE 1:
PB0_ANA0 PB1_ANA1
C11 C11
0.001uF 0.001uF
Note 2: The XP supports internal, external crystal, external
C20 Y1
ceramic resonator, external R/C and external CMOS drive
clock modes. R14, R15, R18, C19, C20 and Y1 are used to
none none
support the clock mode selected.
Yes Yes shipped configured for external 20MHz ceramic resonator or
internal clock operation. When using Internal oscilator,
none Yes
pins 7 and 8 could be used as GPIO ports PA0 and PA1. To do
so install R20 and R21.
none none
Table 2 shows the recommended clock mode configurations.
®
F08xA Series MCU Development Board, Page 1 of 2
Note 1:
PB6 and PB7 are dual function pins (GPIO or Analog
R12, R13, R16, and R17 are zero-ohm resistors used in
conjunction with GPIO Control Registers to select function
desired. C21, C22, and C23 are bypass capacitors that are used
for better noise rejection. U8 is an optional filter that can
be used to improve the quality of the Analog Supply. The
development board is shipped configured for Analog Supply.
Table 1 shows the configurations recommended
TABLE 1
R12 R13 R16 R17 R22
GPIO OUT IN OUT IN IN
Analog IN OUT IN OUT OUT
Supply
SW1 SW1
GND
RESET/TEST2
R13 R13
PB6
R22 R22
0 0
0 0 PB5_JP
28 pin footprint
U5 U5
PB2_ANA2
1
PB2/ANA2 PB1/ANA1
PB4_ANA7
2
PB4/ANA7 PB0/ANA0
PB5
3
PB5/Vref PC3/COUT/LED
PB3_ANA3
4
PB3/ANA3/CLKIN PC2/ANA6/LED
5
PB6(AVDD) PC1/ANA5/CINN/LED
VCC_33V
6
VDD PC0/ANA4/CINP/LED
PA0_T0IN
7
PA0/T0IN/T0OUTXIN DBG
PA1_T0OUT
8
PA1/T0OUT/XOUT RESET/PD0
GND
9
GND PC7/LED
10
PB7(AGND) PC6/LED
PA2
11
PA2/DE PA7/T1OUT
PA3_CTS0
12
PA3/CTS0 PC5/LED
PA4_RXD0
13
PA4/RXD0 PC4/LED
PA5_TXD0
14
PA5/TXD0 PA6/T1IN/T1OUT
Z8F04xA_28 Z8F04xA_28
PB7
PB2_ANA2 PB3_ANA3 PC0_ANA4 PC1_ANA5 PC2_ANA6
C12 C12 C13 C13 C14 C14 C15 C15 C16 C16
0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF 0.001uF
PB0_ANA0
PB1_ANA1
PB2_ANA2
PB3_ANA3
PC0_ANA4
PC1_ANA5
The development board is
PC2_ANA6
PB4_ANA7
®
Z8 Encore! XP F08xA Series Development Kit
If Module is plugged onto the Dev Platform the local
supply)
RS232 interface is disabled by pin 50 of JP2
JP2 JP2
PB4_ANA7
1
PC1_ANA5
3
PB3_ANA3
5
PB1_ANA1
7
VCC_33V
9
PC4
11
PC7
13
PC3_COUT
15
PA6_nT1OUT
17
GND
19
PA7_T1OUT
U8 C21...C23 21
23
25
OUT OUT
27
29
optional IN
31
PA3_CTS0
33
PA4_RXD0
35
37
GND
39
41
43
R19 10K R19 10K
PB6
45
PB7
47
49
JP5 JP5 51
-RESET
53
1
VCC_33V
55
2
57
VCC_33V
HEADER 2 HEADER 2 59
PB1_ANA1 HEADER 30x2/SM HEADER 30x2/SM
28
PB0_ANA0
27
PC3_COUT
26 connector 1
PC2_ANA6
25
PC1_ANA5
24
for
PC0_ANA4
23
DBG
22
DBG
PD0 reference
21
PC7
20
PC6
19
only
PA7_T1OUT
18
PC5
17
PC4
16 1
PA6_nT1OUT
15 3
-TRSTN
5
-F91_WE
7
GND
9
A6
11
A10
13
GND
15
A8
17
A13
19
A15
21
A18
23
A19
25
PB4_ANA7 A2
27
A11
29
A4
31
C17 C17 C18 C18 A5
33
0.001uF 0.001uF 0.001uF 0.001uF
35
A21
37
GND A22
39
-CS0
41
-CS2
43
D1
45
D3
47
J2 J2
D5
49
D7
51
-MREQ
1 2 53
GND
3 4 55
-WR
5 6 57
-BUSACK
7 8 59
9 10
11 12
13 14
15 16
HEADER 8X2 HEADER 8X2
Title Title Title
XP 4K MDS Processor Module. Schematic. XP 4K MDS Processor Module. Schematic. XP 4K MDS Processor Module. Schematic.
Size Size Size Document Number Document Number Document Number
B B B 96C0941-001 96C0941-001 96C0941-001
Date: Date: Date: Wednesday, July 21, 2004 Wednesday, July 21, 2004 Wednesday, July 21, 2004
User Manual
13
connector 2
PC2_ANA6
2
PC0_ANA4
4
PB2_ANA2
6
PB0_ANA0
8
GND
10
PC5
12
PC6
14
PB5_JP
16
PA0_T0IN_JP
18
PA1_T0OUT_JP
20
PA2
22
24
26
PD0
28
GND
30
32
34
PA5_TXD0
36
38
40
42
44
46
GND
48
50
-DIS_232
-DIS_IrDA
52
-DIS_IRDA
54
GND
56
58
60
JP1 JP1
2
4
6
8
VCC_33V
10
A0
12
A3
14
VCC_33V
16
A7
18
A9
20
A14
22
A16
24
GND
26
A1
28
A12
30
A20
32
A17
34
-DIS_FLASH
36
VCC_33V
38
A23
40
-CS1
42
D0
44
D2
46
D4
48
GND
50
D6
52
-IOREQ
54
-RD
56
-INSTRD
58
-BUSREQ
60
HEADER 30x2/SM HEADER 30x2/SM
Rev Rev Rev
C C C
Sheet Sheet Sheet 1 1 1 of of of 2 2 2