Power And Communication Interfaces; External Interface Headers Jp1 And Jp2 - ZiLOG Z8 Encore! XP F08 A Series User Manual

Z8 Encore! XP
User Manual
10

Power and Communication Interfaces

Table 1. Jumpers JP3 and JP4

External Interface Headers JP1 and JP2

F08xA Series Development Board
®
F08xA Series Development Kit
cost, point-to-point communication between PCs, PDAs, cell phones,
printers and other infrared enabled devices.
Table 1 provides jumper information concerning the shunt status, func-
tions, devices and defaults affected of jumpers JP3 and JP4.
Jumper Status
JP3* OUT
JP3 IN
JP4* OUT
JP4 IN
JP5 OUT
JP5 IN
Note: * These jumpers must not be OUT at the same time
External interface headers JP1 and JP2 are shown in the schematic on
page 13.
Device
Affected Status
RS-232 Enabled
interface
RS-232 Disabled
interface
IrDA interface Enabled
IrDA interface Disabled
U5 RESET/ PD0 (GPIO)
PD0
U5 RESET/ RESET when
PD0 SW1 pressed
Default
X
X
X
UM018603-1005