Linear Technology DC1369A Demo Manual

LTC2260-14/-12, LTC2259-14/-12, LTC2258-14/-12, LTC2257-14/-12,
LTC2256-14/-12, 14/12-Bit, 25Msps to 150Msps ADCs
Description
Demonstration circuit 1369A supports a family of
14/12-bit 25Msps to 150Msps ADCs. Each assembly
features one of the following devices: LTC2262-14 or
LTC2262-12, LTC2261-14, LTC2261-12, LTC2260-14,
LTC2260-12, LTC2259-14, LTC2259-12, LTC2258-14,
LTC2258-12, LTC2257-14, LTC2257-12, LTC2256-14,
LTC2256-12, high speed, high dynamic range ADCs.
Demonstration circuit 1369A supports the LTC2261 family
DDR LVDS output mode. This family of ADCs is also sup-
ported by demonstration circuit 1370A, which is compatible
with CMOS and DDR CMOS output modes.
performance summary
Table 1
PARAMETER
Supply Voltage – DC1369A
Analog Input Range
Logic Input Voltages
Logic Output Voltages (Differential)
Sampling Frequency (Convert Clock Frequency)
Convert Clock Level
Convert Clock Level
Resolution
Input Frequency Range
SFDR
SNR
DEMO MANUAL DC1369A
LTC2262-14/-12, LTC2261-14/-12,
Several versions of the 1369A demo board supporting the
LTC2261 14/12-bit series of A/D converters are listed in
Table 1. Depending on the required resolution and sample
rate, the DC1369A is supplied with the appropriate ADC.
The circuitry on the analog inputs is optimized for analog
input frequencies from 5MHz to 170MHz. Refer to the
data sheet for proper input networks for different input
frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and PScope
and QuikEval are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
(T = 25°C)
A
CONDITION
Depending on sampling rate and the A/D converter
provided, this supply must provide up to 250mA
Depending on SENSE Pin Voltage
Minimum Logic High
Maximum Logic Low
Nominal Logic Levels (100Ω Load, 3.5mA Mode)
Minimum Logic Levels (100Ω Load, 3.5mA Mode)
See Table 1
Single-Ended Encode Mode (ENC – Tied to GND)
Differential Encode Mode (ENC – Not Tied to GND)
See Table 1
See Table 1
See Applicable Data Sheet
See Applicable Data Sheet
VALUE
Optimized for 3.6V
3.5V ↔ 6.0V Min/Max
1V to 2V
P-P P-P
1.3V
0.6V
350mV/1.25V Common Mode
247mV/1.25V Common Mode
0V to 3.6V
0.2V to 3.6V
dc1369af
1