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Debugging SX Devices Using Silicon Explorer II
SX Diagnostic Pin Consideration
SX Dedicated
JTAG Mode
22
To place the IEEE 1149.1 (JTAG) and probe pins (TDI, TCK, TMS,
TDO, PRA and PRB) in the desired mode, select the appropriate check
boxes in the "Device Variations" dialog window (as shown in Figure
9). This dialog window is accessible through the Design Setup Wizard
under the Option menu in Designer.
Figure 9. Diagnostic Pins Configuration
To Access the Device Variations Dialog Box in Designer:
1. Launch Designer.
2. Open your Design.
3. Select Device Setup under the Options Menu. The Device
Selections dialog box appears.
4. Click Next. The Device Variations Dialog Box appears.
When you select the "Reserve JTAG Pin" box, you place the FPGA in
Dedicated JTAG mode, which configures TDI, TCK, and TDO pins for
JTAG boundary scan or in-circuit debug with Silicon Explorer II. Also,
you enable an internal pull-up resistor on both the TMS and TDI pins
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