Conditioned Diphase Encoding; Specifying The Clock Frequency - Viavi MSAM Manual

Conditioned Diphase encoding

In Conditioned Diphase encoding, the phase transition for each bit is determined by the
phase transition for the previous encoded bit.
• Each time the data signal is a logic level 0, the phase transition is the same as
that for the previous encoded bit.
–
a high to low phase transition.
–
a low to high phase transition.
• Each time the data signal is logic level 1, the phase transition is inverted.
–
to high phase transition (
–
high to low phase transition (
See Figure 6
101001100.
Figure 6
The signal level changes occur at the one half bit interval point.

Specifying the clock frequency

The first step in Diphase testing is to specify the clock frequency for the instrument in
Kilohertz.
To specify the clock frequency
1 Select the Setup soft key, then select the Timing setup tab.
2 Specify the frequency in Kilohertz.
The frequency is specified.
January 2016
If the previous bit used a high to low phase transition (
If the previous bit used a low to high phase transition (
If the previous bit used a high to low phase transition (
If the previous bit used a low to high phase transition (
for an illustration of a Conditioned Diphase encoded bit pattern of

Conditioned Diphase encoding

Data Communications and Diphase Testing Manual
).
).
21148872, Rev. 002
Chapter 3 Diphase Testing
Conditioned Diphase encoding
), the 0 is also encoded using
), the 0 is also encoded using
), the 1 is encoded using a low
), the 1 is encoded using a
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