Bootstrap Microprocessor Operation; Audio And Signalling Circuits; Audio Signalling Filter Ic (Asfic); Audio Ground - Motorola MCS 2000 Service Instructions Manual

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Bootstrap Microprocessor Operation

The bootstrap mode of operation is only used to load new software into the FLASH EEPROM
(U0106 or U0102). The MODA (U0103-33) and MODB (U0103-32) inputs must be a logic 0 when the
microprocessor comes out of reset. The microprocessor will wait to receive data on its SCI RX
(U0103-63) line and as data is received, it will be echoed on the SCI TX (U0103-64) line. For
example, when the Smart RIB (SRIB) is used to load new software into the FLASH EEPROM, the
signals to the microprocessor are automatically controlled by the SRIB to enter this mode. First the
SRIB brings the SCI RX DATA (J0403-19) above 12 volts. This turns on dual transistor Q0103 to
bring the MODA and MODB lines and the SCI SELECT line to a logic 0. The SRIB then releases the
LH RESET (J0403-17) line and begins transferring the data to the radio. Data from the SRIB goes to
GP I/O 4 (J0403-20) and data to the SRIB comes from the BUS+ and BUS- lines (J0403-6 and
J0403-18). After an initial data transfer, the SRIB will bring the Vpp line (J0403-21) to 12.5 volts and
start loading the data to be stored in the FLASH. The microprocessor will verify that each of the
FLASH EEPROM memory locations are programmed correctly.

Audio and Signalling Circuits

(Refer to ASFIC schematic page 10-27 for reference)

Audio Signalling Filter IC (ASFIC)

The ASFIC has 4 functions;
1. RX/TX audio shaping, i.e. filtering, amplification, attenuation
2. RX/TX signalling, PL/DPL/HST/MDC/MPT
3. Squelch detection
4. Microprocessor clock signal generation (see Microprocessor Clock Synthesizer Description
Block).
The ASFIC is programmable through the SPI BUS (U0200-E3/F1/F2), normally receiving 21 bytes.
This programming sets up various paths within the ASFIC to route audio and/or signalling signals
through the appropriate filtering, gain and attenuator blocks. The ASFIC also has 6 General Control
Bits GCB0-5 which are CMOS level outputs. In this radio all, except GCB2 used for AUX TX IN2 (see
Aux TX), are used to control the Hear Clear IC. (See Hear Clear Description Block for details).

Audio Ground

(Refer to schematic page 10-29 for reference)
VAG is the dc bias used as an audio ground for the op-amps that are external to the Audio Signalling
Filter IC (ASFIC). U0201 forms this bias by dividing 9.3 V with R0206 and R0207 and buffering the
4.65 V result with a voltage follower. VAG emerges at pin 1 of U0201. C0235 is a bypass capacitor
for VAG. The ASFIC generates its own 2.5 V bias for its internal circuitry. C0210 is the bypass for the
ASFIC's audio ground dc bias. Note that while there are ASFIC VAG, BOARD VAG (U0201), and
Hear Clear VAG, each of these are separate. They do not connect together.
December 6, 2004
Controller Section Theory of Operation: Audio and Signalling Circuits
68P81083C20-D