Pin Assignments - Teac PL-D200V Service Manual

HY57V641620D (64M SDRAM : IC51)

PIN ASSIGNMENTS

(TOP VIEW)
PIN DESCRIPTIONS
PIN
CLK Clock
CKE Clock Enable
CS Chip Select
BA0,BA1 Bank Address
A0 ~ A11 Address
Row Address Strobe,
RAS, CAS, WE Column Address Strobe,
Write Enable
LDQM, UDQM Data Input/Output Mask
DQ0 ~ DQ15 Data Input/Output
V /V Power Supply/Ground
DD SS
V /V Data Output Power/Ground
DDQ SSQ
NC No Connection
106
V 1
DD
DQ0 2
V 3
DDQ
DQ1 4
DQ2 5
V 6
SSQ
DQ3 7
DQ4 8
V 9
DDQ
DQ5 10
DQ6 11
V 12
SSQ
DQ7 13
V 14
DD
LDQM 15
/WE 16
/CAS 17
/RAS 18
/CS 19
BA0 20
BA1 21
A10/AP 22
A0 23
A1 24
A2 25
A3 26
V 27
DD
PIN NAME
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
54
53
52
51
50
49
48
47
46
45
44
43
42
54pin TSOP II
400mil x 875mil 41
0.8mm pin pitch
40
39
38
37
36
35
34
33
32
31
30
29
28
DESCRIPTION
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS