Block Diagram - Teac PL-D200V Service Manual

BLOCK DIAGRAM

Clock control
X0, X1 RSTX
5
X0, X1A
2
EI OS
Communication
prescaler
SIN0
SOT0
SCK0
I/O expanded
SIN1, 2
SOT1, 2
interface x 2
SCK1, 2
AVCC
A/D converter
AVRH. L
(10 bits)
AVSS
ADTG
AN0 to 7
PWC0
16-bit PWC
PWC1
3 channels
PWC2
8
P00
P07
circuit
F
RAM
ROM
2
UART
serial
channels
8 8 8
P10 P20 P30
P17 P27 P37
CPU
core
2
MC-16LX family
r
I/O port
8 8 8
P40 P50 P60
P47 P57 P67
Interrupt controller
8-/16-bit PPG
8-/16-bits UD counter
µPG
Chip select
I/O timer
16-bit input capture x 2
3, 4, 5
16-bit output conveyer x 6
TIN0
16-bit free-run timer
16-bit reload tim
x 2 channels
2
I C interface
External interrupt
8 8 8 4
P70 P80 P90 PA0
P77 P87 P97 PA3
PPG0, 1
PPG2, 3
PPG4, 5
AIN0, 1
BIN0, 1
ZIN0, 1
EXTC
MT00
MT01
CS0, 1, 2, 3
IN0, 1
OUT0, 1, 2,
3,4,5
TOT0
SCL
SDA
8
IRQ0 to 7
91