Table of Contents
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Name
Number
YUV1
VREF
YUV2
CDAC
YUV3
COMP
YUV4
RSET
ADVEE
YUV5
YDAC
YUV6
VDAC
YUV7
CAMIN3
PCLK2XSCN
CAMIN4
PCLKQSCN
CAMIN5
VSYNC#
CAMIN6
HSYNC#
CAMIN7
HD[5:0]
127:122
DCI[5:0]
AUX1[5:0]
HD[6]
DCI[6]
AUX1[6]
VFD_DOUT
HD[7]
DCI[7]
AUX1[7]
VFD_DIN
HD[8]
DCI_FDS#
AUX2[0]
VFD_CLK
HD[9]
AUX2[1]
SQSQ
HD[10]
AUX2[2]
SQSK
100
I/O
Definition
107
O
YUV1 pixel output data.
I
Internal voltage reference to video DAC. Bypass to ground with 0.1 F capacitor.
O
YUV2 pixel output data.
108
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
109
O
YUV3 pixel output data.
I
Compensation input. Bypass to ADVEE with 0.1 F capacitor.
110
O
YUV4 pixel output data.
I
DAC current adjustment resistor input.
111
I
Analog power for video DAC.
113
O
YUV5 pixel output data.
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
114
O
YUV6 pixel output data.
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
115
O
YUV7 pixel output data.
I
Camera YUV 3.
116
I/O
27-MHz video output pixel clock.
I
Camera YUV 4.
117
O
13.5-MHz video output pixel clock.
I
Camera YUV 5.
118
I/O
Vertical sync, active low.
I
Camera YUV 6.
119
I/O
Horizontal sync, active low.
I
Camera YUV 7.
I/O
Host data I/O [5:0].
I/O
DVD channel data I/O [5:0].
I/O
Aux1 data I/O [5:0].
I/O
Host data I/O [6].
I/O
DVD channel data I/O [6].
128
I/O
Aux1 data I/O [6].
I
VFD data output.
I/O
Host data I/O [7].
I/O
DVD channel data I/O [7].
131
I/O
Aux1 data I/O [7:0].
I
VFD data input.
I/O
Host data bus 8.
I/O
DVD input sector start.
132
I/O
Aux2 data I/O 0.
I
VFD clock input.
I/O
Host data bus line 9.
133
I/O
Aux2 data I/O [1] when selected.
I
Subcode-Q data.
I/O
Host data bus line10.
134
I/O
Aux2 data I/O [2] when selected.
I
Subcode-Q clock.
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