Teac PL-D200V Service Manual page 84

Name Number
MCLK 39
TBCK 40
SPDIF 41
SEL_PLL3
NC 42, 48
RSD 45
RWS 46
RBCK 47
XIN 49
XOUT 50
AVEE 51
DMA[11:0] 66:61, 58:53
DCAS# 69
DOE# 70
DSCK_EN
DWE# 71
DRAS# 72
DMBS0 73
DMBS1 74
DB[15:0] 96:93, 90:85,
82:77
DCS[1:0]# 97,100
DQM 101
DSCK 102
DCLK 105
YUV0
CAMIN2
UDAC
106
I/O
I/O Audio master clock for audio DAC.
O Audio transmit bit clock.
O S/PDIF output.
I Clock source select.
SEL_PLL3
0
1
No connect pins. Leave open.
I Audio receive serial data.
I Audio receive frame sync.
I Audio receive bit clock.
I Crystal input.
O Crystal output.
I Analog power for PLL.
O DRAM address bus [11:0].
O DRAM column address strobe.
O DRAM output enable.
O DRAM clock enable.
O DRAM write enable.
O DRAM row address strobe.
O SDRAM bank select 0.
O SDRAM bank select 1.
I/O DRAM data bus [15:0].
O SDRAM chip select [1:0].
O Data input/output mask.
O Output clock to SDRAM.
I 27 MHz clock input to PLL.
O YUV0 pixel output data.
I Camera input 2.
O Video DAC output.
Mode
A
B
C
D
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
Definition
Clock Source
Crystal oscillator
DCLK input
YDAC UDAC VDAC
Y C Composite
Y Composite Composite
Y U Composite
Y U
CDAC
C
C
V
C V
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