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26
3.5 Communication Methods
Event Registers
Standard Event Status Register (SESR) ____________________________
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A standard event status register is an 8-bit register.
If any bit in the Standard Event Status Register is set to 1 (after masking by the
Standard Event Status Enable Register), bit 5 (ESB) of the Status Byte Register
is set to 1.
See:
"Standard Event Status Enable Register (SESER)" (p.27)
The standard event status register is cleared at the following times:
*CLS
• When a "
" command is executed
ERR?
• When a "
" command is executed
• When the device is powered on
PON
Power-On Flag
Set to 1 when the power is turned on, or upon recovery from an outage.
URQ
User Request
unused
CME
Command error (The command to the message terminator is ignored.)
This bit is set to 1 when a received command contains a syntactic or semantic
error:
•
Program header error
•
Incorrect number of data parameters
•
Invalid parameter format
•
Received a command not supported by the device
EXE
Execution Error
This bit is set to 1 when a received command cannot be executed for some
reason.
•
The specified data value is outside of the set range
•
The specified setting data cannot be set
•
Execution is prevented by some other operation being performed
DDE
Device-Dependent Error
This bit is set to 1 when a command cannot be executed due to some reason
other than a command error, a query error or an execution error.
•
When the command cannot be executed because there is an internal
anomaly
QYE
Query Error (the output queue is cleared)
This bit is set to 1 when a query error is detected by the controller of the output
queue.
•
When an attempt has been made to read an empty output queue (GP-IB
only)
•
When the data overflows the output queue
•
When data in the output queue has been lost
RQC
Request Control
unused
OPC
Operation Complete
This bit is set to 1 in response to an "
•
It indicates the completion of operations of all messages up to the "
command
*OPC
" command.
*OPC
"
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