Table of Contents
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JTAG/ISP Chain
CN3
PF_TDI
PF_TDO(PF->FPGA)
CPLD
FPGA
EPR2
CN
PF_TDI
1
EPR CN
EPCS64
0
PF_TDO
+3.1V
IC10
R1173H001D-T1-F
R75
0
4
0
3
VDD
5
CE
VOUT
R73
2.2k
1
ADJ
GND
1.0V
2
R74
C51
C50
1k
10uF
10uF
2012
2012
GND
2
+3.1V
001
PWRGD
001
LCD2_CONT
3
L2_RESET
L2_SDI
L2_SCL
L2_CS
R77
10
CLOCK
002
CLK_SYS
Pacific_CONT
R1
47
FPGA_OUT_B[6]
FPGA_OUT_B[5]
FPGA_OUT_B[7]
FPGA_OUT_B[1]
FPGA_OUT_B[2]
FPGA_OUT_B[0]
001
FPGA_TO_CPLD
FPGA_OUT_B[4]
FPGA_OUT_B[3]
002
RST_PLL2_X
PLL CONTROL
002
RST_PLL1_X
CL2
FPGA_OUT_H
FPGA_OUT_H
CL1
0.8
FPGA_OUT_V
FPGA_OUT_V
4
FPGA_OUT_CLK
002
RST_X
RESET
002
SRST_X
R2
10
CPU_CLK
CPU_DATA[9]
CPU_DATA[5]
CPU_DATA[14]
CPU_DATA[12]
CPU_DATA[6]
CPU_DATA[10]
CPU_DATA[15]
CPU_DATA[7]
CPU_DATA[13]
CPU_DATA[2]
CPU_DATA[11]
CPU_DATA[0]
CPU_DATA[1]
CPU_DATA[8]
CPU_DATA[4]
CPU_DATA[3]
001
XRESET
5
CPU_CS_X
A
B
R9
68k
TPS54610PWPR
28
RT
27
SYNC
0
26
+3.1V
SS/ENA
25
VBIAS
24
VIN5
FPGA bord
L1
23
10uH
VIN4
22
VIN3
21
VIN2
20
VIN1
+3.1-1V
19
C1
C2
C5
PGND5
22uF
C3
C4
Pacific
18
10uF
0.01uF
0.01uF
1uF
6.3V
PGND4
17
PGND3
16
PGND2
C52
15
PGND1
1uF
C53
GND
C54
22uF
0.1uF
6.3V
2012
C
001
PACIFIC_CONT_H_ACT
H:ENABLE L:SAVE
PR-312
CN1
178555121
JACK
+3.1V
1
2
+2.5V
3
4
+3.1V
+2.5V
+3.1V
5
6
+1.8V
+3.1V
7
8
+1.8V
9
10
+1.8V
+3.1V
+3.1V
11
12
+1.8V
PWRGD
13
14
GND
GND
15
16
GND
GND
17
18
GND
GND
19
20
GND
OSD_BLK
L2_RESET
21
22
OSD_BLK
OSD_D[3]
L2_SDI
23
24
OSD_D[3]
OSD_D[0]
L2_SCL
25
26
OSD_D[0]
OSD_D[2]
L2_CS
27
28
OSD_D[2]
R8
0
OSD_D[1]
GND
29
30
CONTRAST
OSD_CLK
CLK_SYS
31
32
OSD_CLK
NC
33
34
GND
R4
0
35
36
GND
TDI(D_G_2)
R5
0
PACIFIC_H_ACT
37
38
TDO(D_G_3)
FPGA_OUT_G[7]
TEMP
39
40
D_G_11
FPGA_OUT_G[6]
D_B_10
41
42
D_G_10
FPGA_OUT_G[5]
D_B_9
43
44
D_G_9
FPGA_OUT_G[4]
D_B_11
45
46
D_G_8
FPGA_OUT_G[2]
D_B_5
47
48
D_G_6
FPGA_OUT_G[1]
D_B_6
49
50
D_G_4
FPGA_OUT_G[0]
D_B_4
51
52
D_G_5
FPGA_OUT_G[3]
D_B_8
53
54
D_G_7
0
R6
D_B_7
55
56
TMS(D_R_3)
R7
0
RST_PLL2_X
57
58
TCK(D_R_2)
FPGA_OUT_R[2]
RST_PLL1_X
59
60
D_R_6
FPGA_OUT_R[1]
GND
61
62
D_R_5
0.8
FPGA_OUT_R[6]
H
63
64
D_R_10
FPGA_OUT_R[4]
65
66
V
D_R_8
FPGA_OUT_R[7]
FLD
67
68
D_R_11
FPGA_OUT_R[3]
GND
69
70
D_R_7
FPGA_OUT_R[5]
RST_X
71
72
D_R_9
FPGA_OUT_R[0]
SRST_X
73
74
D_R_4
GND
75
76
GND
CPU_BE_L_X
CPU_CLK
77
78
CPU_BE_L_X
CPU_BE_U_X
CLK_IF
79
80
CPU_BE_U_X
CPU_OE_X
CPU_DATA_9
81
82
CPU_OE_X
CPU_ADRS[7]
CPU_DATA_5
83
84
CPU_ADRS_7
CPU_ADRS[13]
CPU_DATA_14
85
86
CPU_ADRS_13
CPU_ADRS[14]
CPU_DATA_12
87
88
CPU_ADRS_14
CPU_ADRS[11]
CPU_DATA_6
89
90
CPU_ADRS_11
CPU_ADRS[4]
CPU_DATA_10
91
92
CPU_ADRS_4
CPU_ADRS[16]
CPU_DATA_15
93
94
CPU_ADRS_16
CPU_ADRS[15]
95
96
CPU_DATA_7
CPU_ADRS_15
CPU_ADRS[3]
CPU_DATA_13
97
98
CPU_ADRS_3
CPU_ADRS[2]
CPU_DATA_2
99
100
CPU_ADRS_2
CPU_ADRS[8]
CPU_DATA_11
101
102
CPU_ADRS_8
CPU_ADRS[17]
CPU_DATA_0
103
104
CPU_ADRS_17
CPU_ADRS[1]
CPU_DATA_1
105
106
CPU_ADRS_1
CPU_ADRS[5]
CPU_DATA_8
107
108
CPU_ADRS_5
CPU_ADRS[12]
CPU_DATA_4
109
110
CPU_ADRS_12
CPU_ADRS[6]
CPU_DATA_3
111
112
CPU_ADRS_6
CPU_ADRS[9]
XRESET
113
114
CPU_ADRS_9
CPU_ADRS[10]
NC
115
116
CPU_ADRS_10
CPU_RW
CPU_CS_X
117
118
CPU_RW
GND
119
120
GND
GND
002
CPU-IF
C
VPR-103 (1/2)
VPR-103 (1/2)
SUFFIX: -12
SUFFIX: -12
PWRGD
001
R10
15k
DC/DC Freq. 600kHz
IC1
1
AGND
2
VSENSE
C10
47pF
3
COMP
0
R11
C11 100pF
4
PWRGD
5
C8
0.0022uF
BOOT
6
C6
0.047uF
R13
R18
PH1
10k
100
7
C9
R19
R22
PH2
1000pF
R14
10k
68k
8
15k
PH3
9
L2
10uH
C12
PH4
0.0022uF
10
PH5
11
R12
R15
+1.0V
PH6
68
330
1000pF
12
C13
PH7
13
PH8
C7
100uF
14
PH9
1.0V
EPAD
29
IC2
R1173H001D-T1-F
R25
0
4
C18
1uF
0
3
VDD
5
CE
VOUT
R26
1.5k
1
ADJ
GND
1.0V
C20
22uF
2
R27
C14
C16
6.3V
10uF
1k
10uF
2012
2012
C
2012
GND
IC3
R1173H001D-T1-F
R28
330
4
C19
0
1uF
3
VDD
5
CE
VOUT
R29
470
1
OSD
002
ADJ
GND
1.0V
C21
22uF
2
C17
R30
6.3V
C15
1k
10uF
10uF
2012
C
2012
2012
GND
0V - 2.0V
R31
2.2k
CONT
R32
R35
150k
47k
R33
R36
15k
47k
GND
PF_TDI(CPLD_OUT)
PF_TDO
PF_TMS
PF_TCK
FPGA_TO_CPLD
001
+3.1V
EPR
+3.1V
R34
R20
R23
R24
CN3
10k
10k
10k
10k
1
VCC
NM
NM
NM
2
TRST
3
TDI
PF_TDI
4
TDO
PF_TDO
5
TMS
PF_TMS
6
TCK
PF_TCK
7
R21
10k
8
GND
NM
Hirose-angle-8p
10 9
GND
GND
4-12
4-12
D
E
Cathode1
001
001
Anode1
+2.5V
001
CPLD_TO_PANEL
C22
0.1uF
RB1
PANEL_IN_R[7]
1
PANEL_IN_R[6]
3
5
PANEL_IN_R[5]
PANEL_IN_R[4]
7
+1.8V
RB2
1
PANEL_IN_R[3]
3
PANEL_IN_R[2]
5
PANEL_IN_R[1]
PANEL_IN_R[0]
7
PANEL_IN_G[7]
RB3
1
PANEL_IN_G[6]
3
PANEL_IN_G[5]
5
PANEL_IN_G[4]
7
+3.1V
RB4
PANEL_IN_G[3]
1
C23
PANEL_IN_G[2]
3
0.1uF
IC9
(2/2)
PANEL_IN_G[1]
5
TC7SZ04FU(TE85R)
C49
PANEL_IN_G[0]
7
0.1uF
VCC
RB5
PANEL_IN_B[7]
1
GND
PANEL_IN_B[6]
3
NM
PANEL_IN_B[5]
5
7
PANEL_IN_B[4]
GND
RB6
1
PANEL_IN_B[3]
001
IC9
(1/2)
3
TC7SZ04FU(TE85R)
PANEL_IN_B[2]
2
4
5
PANEL_IN_B[1]
PANEL_IN_B[0]
7
NM
R70
0
10
R71
PANEL_IN_CLK
R68
47
PANEL_IN_V
R69
47
PANEL_IN_H
+3.1V
001
IC8
L7
+2.8V
R1173H001D-T1-F
1uH
001
2016
R65
330
4
C46
001
1uF
3
VDD
5
001
CE
VOUT
R66
1.5k
1
ADJ
GND
1.0V
C47
22uF
2
R67
C44
C45
6.3V
10uF
1k
2012
10uF
2012
2012
C
GND
001
001
001
001
F
LCD2_CONT
001
FPC
HRS FH12 Angle
1-778-451-31
CN4
Cathode2
1
Anode2
2
Cathode1
3
Anode1
4
GND
5
0.8
CL4
RSVD
6
0.8
CL5
RSVD
7
0.8
CL6
RSVD
8
0.8
CL7
RSVD
9
+3.1V
GND
10
VCCIO
11
L2_CS
/CS
12
0.8
CL8
RSVD
13
L2_SDI
SI
14
L2_SCL
SCL
15
GND
16
47
2
D27
17
4
D26
18
6
D25
19
8
D24
20
2
47
D23
21
4
D22
22
6
D21
23
8
D20
24
2
47
D17
25
4
D16
26
6
D15
27
8
D14
28
47
2
D13
29
4
D12
30
6
D11
31
8
D10
32
47
2
D07
33
4
D06
34
6
D05
35
8
D04
36
2
47
D03
37
4
D02
38
6
D01
39
8
D00
40
GND
41
CLK
42
VSYNC
43
HSYNC
44
L2_RESET
/RESET
45
+6.5V
GND
46
VPC
47
VCC
48
VCC
49
GND
50
51
52
GND
C48
0.1uF
E1
GND
HDVF-C30WR
G
H
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