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ON Semiconductor ALPINE NCRHA926 User Manual

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Evaluation Board
User's Manual
ALPINE (NCRHA926)
Introduction
The Alpine Evaluation Module (Alpine EVM) is an ARM
926EJ−S Processor based SoC targeted towards space−based
applications. This EVM can be used for application development
based on ARM core.
The Alpine EVM has major peripherals to create a space−based
application, formidable for single−board testing environment.
Key Features
The Alpine is a high−performance and low−power platform that
enables users to evaluate and develop space communication
applications with Alpine SoC from ON Semiconductor. The Alpine
EVM has the following key features:
•
Alpine SoC−LGA564
♦
SDRAM
♦
FLASH
♦
GR1553B
♦
SPI
♦
SpaceWire
♦
CAN 2.0 Controller
♦
UART TO USB
♦
External AHB through FMC Connector
⋅ Mezzanine (Daughter card) or
⋅ Main Board Connector Options
♦
Mounting option of Yamaichi socket TCBGA564.
•
Alpine SoC Test Ports
♦
Alpine JTAG
®
♦
ARM
926EJ−S Processor Debug
•
On−Board Oscillators
♦
100 MHz for System Clock
⋅ 50 MHz for SpaceWire clock (Derived form System Clock
Regulator)
⋅ 25 MHz for SPI External clock (Derived form System Clock
Regulator)
♦
20 MHz for MIL1553 Clock
•
Off−Board/External Clocking Support
♦
System Clock
♦
SpaceWire CLK
♦
SPI External Clock
♦
GR1553B Clock
•
General User I/O's
♦
16 General Purpose IO's can be configured with External
Connection Option through Header
♦
8 LEDS Configuration
♦
8 DIP Switches
•
SPI Peripherals
♦
SD Card
♦
Temperature Sensor
♦
ADC 8 Channels
© Semiconductor Components Industries, LLC, 2020
December, 2020 − Rev. 0
®
EVAL BOARD USER'S MANUAL
1
www.onsemi.com
Publication Order Number:
EVBUM2724/D

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Summary of Contents for ON Semiconductor ALPINE NCRHA926

  • Page 1 Key Features The Alpine is a high−performance and low−power platform that enables users to evaluate and develop space communication applications with Alpine SoC from ON Semiconductor. The Alpine EVM has the following key features: • Alpine SoC−LGA564 ♦...
  • Page 2 ALPINE (NCRHA926) • External Interface Headers ♦ CAN 2.0 9−Pin D−SUB Male−2 Ports ♦ GR1553B BNC −2 Ports ♦ SpaceWire 9−pin D−SUB Male −2 Ports ♦ USB TO UART Micro USB Type B ♦ Micro SD connector ♦ ADC SMA connectors – 8no’s •...
  • Page 3 ALPINE (NCRHA926) Functional Block Diagram Figure 1 shows the functional block diagram of the Alpine EVM. Figure 1. Alpine Functional Block Diagram www.onsemi.com...
  • Page 4 ALPINE (NCRHA926) Memory Map Table 1. MEMORY MAP Module Map #0 Start Address Map #0 End Address Map #1 Start Address Map #1 End Address External MRAM 0x0000_0000 0x007F_FFFF 0x5000_0000 0x507F_FFFF External SDRAM 0x4000_0000 0x7FFF_FFFF 0x0000_0000 0x3FFF_FFFF 0x8000_0000 0x8000_00FF 0x4000_0000 0x4000_00FF 0x8000_0100 0x8000_03FF...
  • Page 5 ALPINE (NCRHA926) Board Layout The Alpine EVM has dimensions of 236.35 mm × 194.69 mm and is a 12−layer board fabricated with FR4 grade material. Figure 2 shows the top view of the Alpine board. Figure 3 shows the bottom view of the Alpine board. Figure 2.
  • Page 6 ALPINE (NCRHA926) Figure 3. Alpine Board (Bottom View) www.onsemi.com...
  • Page 7 ALPINE (NCRHA926) Hardware Setup Below are the instructions to set up the Alpine EVM. 1. Before power up the board insert jumpers J41, J43, J49 and J58. ® ® 2. Connect 20 Pin SEGGER J−LINK PUS Adapter JTAG to J65 (ARM 926EJ−S Processor JTAG) on the Alpine EVM as per below Figure 4.
  • Page 8 ALPINE (NCRHA926) Figure 5. Alpine Serial Port Connection Software Setup Installation Guidelines a. Download the latest version of JFlash.exe from the below link and install it. https://www.segger.com/downloads/jlink/#J−LinkSoftwareAndDocumentationPack b. Open README.txt from JFLASH folder(attached) and follow the instruction. c. Extract the u−boot.bin and alpine.bin from the images directory of the Alpine SDK alpine_sdk_v1p0.tar.gz d.
  • Page 9 ALPINE (NCRHA926) • Navigate to <Installation>\JLink_V640\Samples\JFlash\ProjectFiles\ONSemi folder and select AlpineV1.jflash file. A copy of the AlpineV1.jflash file can be located in the Alpine SDK jflash directory. Figure 7. f. Open u−boot.bin • File → Open data file ( Ctrl+O ) and open u−boot.bin file. Figure 8.
  • Page 10 ALPINE (NCRHA926) g. Program the target: • Target → Production Programming (F7) Figure 10. • Wait for flashing to complete Figure 11. h. After successful programming of u−boot.bin close and reopen J−Flash and repeat steps ‘e’, ‘f’ and ‘g’ with start address in step ‘f’...
  • Page 11 ALPINE (NCRHA926) i. After successful programming of u−boot.bin and alpine.bin, power cycle the board. j. Below is the LED pattern, • Uboot starts booting: All LED’s will be in OFF state. • Uboot up and running: LED1 and LED2 will toggle upon UART receive and transmit activity. •...

  • Page 12: Interface Details

    ALPINE (NCRHA926) INTERFACE DETAILS Clock Distribution Figure 14 shows the clock distribution circuit. One 100−MHz and 20 MHz oscillator used on board. 100−MHz oscillator is for Alpine system clock, the 20 MHz oscillator is for mil1553 clock input and for remaining interfaces clock is divided from 100−MHz oscillator using clock dividers.
  • Page 13 ALPINE (NCRHA926) Reset Circuit Distribution The Alpine EVM features power on reset and push button reset (MR) for resetting the Alpine SoC device. TPS3802K33DCKR supervisory circuit monitors 3.3 V, when the voltage drops below 2.93 V it provides reset signal to the system.
  • Page 14 ALPINE (NCRHA926) Memory Interface SDR−SDRAM Interface The Alpine EVM features dual configurations of SDRAM, which are factory configurable as shown in Figure 16. Below are the details of the configurations, • 640 Mb (16Mx32 Data & 16Mx8 ECC bits) of SDRAM using two SDRAMs according to the below configurations ♦...
  • Page 15 ALPINE (NCRHA926) FLASH Interface The Alpine EVM features dual configurations of Boot Memory through MRAM controller which are factory configurable. Below are the details of the configurations, • 64 Mb NOR Flash ♦ 8/16 Bit configurable • 64 Mb MRAM – Optional Device ALPINE NOR FLASH (4Mx16) S29GL064S70DHI040...

  • Page 16: Can Interface

    ALPINE (NCRHA926) GR1553B Interface Alpine EVM features dual redundant GR1553B bus. Key features of this interface are • Bus Controller (BC), Remote Terminal (RT) and Bus Monitor (BM) modes of operation. • All transfer types supported, including RT−to−RT and broadcast transfers. •...
  • Page 17 ALPINE (NCRHA926) SpaceWire Interface The Alpine EVM features two ports of SpaceWire interface. SpaceWire data lines are converted to LVDS using Quad LVDS driver & Quad LVDS receiver and terminated two independent 9 pin d−sub connector. All differential lines are trace length matched and PCB tracks have a 100 W differential impedance.

  • Page 18: Fmc Connector

    ALPINE (NCRHA926) External AHB Interface The Alpine EVM features AHB interface through external FMC connector. FMC Connector I/O Voltage can be either set to 1.8 V or 3.3 V depending on the jumper setting. SN74AVC16T245DGGR shall be used for voltage level shifting between 3.3 V to 1.8 V.

  • Page 19: Gpio Interface

    ALPINE (NCRHA926) GPIO Interface The Alpine EVM features 16 GPIO’s. The GPIO lines are jumper configurable to take multiple configurations. • GPIO [15:8] lines can be configured as either to take input from slide switch or connected to FMC connector through a level translator.

  • Page 20: Spi Interface

    ALPINE (NCRHA926) SPI Interface The Alpine EVM has one SPI port with 4 Slave selection lines refer Figure 24. SPI lines are terminated to four headers (SPI00 to SPI03) for external interface. SPI lines are also connected to below configuration through jumper selection. Temperature Sensor is located on the bottom side of the PCB underneath the Alpine to monitor device temperature.
  • Page 21 ALPINE (NCRHA926) ALPINE CONNECTOR, JUMPER & HEADER DETAILS The Alpine EVM has several connectors that provide access to various interfaces on the board; Table 5 lists these connectors. Table 5. ALPINE CONNECTORS Board Reference Part Number Pins Function TST−110−01−L−D Alpine JTAG ®...
  • Page 22 ALPINE (NCRHA926) Alpine JTAG Header (J64) Table 6. ALPINE JTAG HEADER PINOUT Pin Number Description Pin Number Description Power supply (3.3 V) Return Test Clock Power supply (3.3 V) Ground Test Reset Test Data Out Ground Ground Test Data In Alpine Reset Ground Ground...
  • Page 23 ALPINE (NCRHA926) CAN Termination Selection Header (JP1) Table 10. CAN TERMINATION HEADER PINOUT Pin Number Description Power supply (3.3 V) Series 62E resistor to CANL pin Power supply (3.3 V) Series 62E resistor to CANH pin Table 11. CAN TERMINATION TYPES Selection Termination Modes 2−4 (Default)
  • Page 24 ALPINE (NCRHA926) LED/GPIO Selection Jumper (J6, J10, J13, J17, J21, J26, J30, J34) Table 13. LED/GPIO JUMPER SELECTION PINOUT Pin Number Description User accessible GPIO (00−07) through FMC−HPC Alpine GPIO (00−07) LED’s (00−07) NOTE: J6, J10, J13, J17, J21, J26, J30, J34 Pin mapping on jumpers are common. Total 8 LED’s or to GPIO connection through FMC −HPC −...
  • Page 25 ALPINE (NCRHA926) Table 16. SYSTEM CLOCK SETTING Position Connection Open (Default) Internal 100 MHz clock Close External clock through SMB connector SPI Clock Selection Jumper (J12) Table 17. SPI CLOCK SELECTION JUMPER PINOUT Pin Number Description Power supply (3.3 V) SPI clock selection Table 18.
  • Page 26 ALPINE (NCRHA926) Alpine Mapping between FLASH/SDRAM (J59) Table 23. REMAP SELECTION JUMPER PINOUT Pin Number Description Power supply (3.3 V) Alpine Remap selection Table 24. REMAP JUMPER SETTING Position Connection Open (Default) FLASH Close SDRAM AHB Signal Voltage Level Selection (J2) Table 25.

  • Page 27: Power Supply Distribution

    ALPINE (NCRHA926) JTAG/M3 Debug Selection (J54) Table 29. JTAG/M3 DEBUG SELECTION JUMPER PINOUT (reserved for future use) Pin Number Description Power supply (3.3 V) JTAG/M3 Debug selection Ground Table 30. JTAG/M3 DEBUG SELECTION JUMPER SETTING (reserved for future use) Position Connection 1−2 M3 Debug...
  • Page 28 ALPINE (NCRHA926) Power Distribution Flow Figure 26. Power Distribution Flow Diagram www.onsemi.com...
  • Page 29 ALPINE (NCRHA926) FMC−HPC CONNECTOR FMC−HPC Pinout Figure 27. FMC−HPC Pinout Table ARM is a registered trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. SEGGER is a registered trademark of SEGGER Microcontroller GmbH & Co. in the EU and/or elsewhere. www.onsemi.com...
  • Page 30 LIMITATIONS OF LIABILITY: ON Semiconductor shall not be liable for any special, consequential, incidental, indirect or punitive damages, including, but not limited to the costs of requalification, delay, loss of profits or goodwill, arising out of or in connection with the board, even if ON Semiconductor is advised of the possibility of such damages. In no event shall ON Semiconductor’s aggregate liability from any obligation arising out of or in connection with the board, under any theory of liability, exceed the purchase price paid for the board, if any.

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