Olympus OEP-3 Service Manual page 117

Synchronous control
The external sync signals (EXT_VD and AFC_HD) and internal sync signals (OVD and OHD (IC401
CXD1217QN)) produced in an analog signal processing block are switched using an SRC/nMEM signal
from CPU (IC501) and sent to the CPU and DRAM control circuit as a V sync signal (SWD_VD) and H
sync signal (SWD_HD). The AFC_HD signal is AFC-processed in the analog signal processing block. If
the AFC processing should be interrupted, the operation of a digital signal processing block is not
guaranteed. The CPU to which the SWD_HD and SWD_VD sync signals were input compares each
phase for VF judgment (frame judgment). This VF judgment performs processing so that the context is
not lost even if a jitter slightly exists in the sync signals. Therefore, odd and even fields are not misplaced
for capturing. The SWD_VD sync signal is also AFC-processed by the software in CPU. Even if noise is
mixed in the SWD_VD sync signal, therefore, the noise component is canceled. A virtual VD signal is
generated by CPU even if the SWD-VD signal is interrupted and even if the period is changed
(CPU_VD). The CPU_VD signal is input to the DRAM control circuit.
Output of blanking signal
The V blanking signal that determines the position of the effective screen in the vertical direction counts
the falling of an SWD_HD signal after an SWD_VD signal is input to CPU, and it is output as a
CPUVBLNKV signal. For the H blanking signal that determines the position of the effective screen in
the horizontal direction, a BLNK signal is output as the blanking signal for input image data capture and
memory image data monitor output operations by the setting value set to the control register of a DRAM
control circuit and the input of a CPUVBLNKV signal.
Control of DRAM control circuit
. Capture operation
. Monitor output operation
. Print data output
. DRAM refresh operation
. Random access operation
To perform the operations described above, each mode is set to the register of a DRAM control circuit.
The DRAM control circuit triggers VD and HD signals for operation.
Each setting is not restricted by video timing. The setting value is latched using a VD signal and
validated after the VD signal.
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OEP-3 V1 (UC)