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Clock Source and Frequency
External Sample Clock
CLK IN
PLL
PXI_CLK10
(None)
© National Instruments Corporation
The NI 5450 has a Sample clock rate of 12.2 kHz to 400 MHz. The timing
of the device is very flexible, and you have multiple choices for deriving
the Sample clock. There are modes for deriving the Sample clock from the
internal Sample clock timebase, as well as modes to provide external
clocks. You also have several choices for providing the frequency
reference for the onboard phase-locked loop.
High
PLL* W
Resolution
with Phase
Oscillator
Adjust
External Sample Clock Timebase
Clocking Options
Waveform generation is driven by the Sample clock; depending on your
application, some sources may be better choices than others. You can use
the following sources for the NI 5450 Sample clock:
•
Internal Sample clock—the onboard clock is used as the Sample clock
source and the Sample clock is derived from the Sample clock
timebase.
•
External Sample clock—the Sample clock has an external source that
derives device clocking by directly driving the DAC and all waveform
generation operations on the device.
•
Reference clock—the Sample clock is derived from an external source
that is phase–locked to the Sample clock timebase. The phase-locked
loop (PLL) Reference clock source specifies the source of the control
voltage that tunes the VCXO of the Sample clock timebase for internal
clock update sources. The PLL circuit adjusts the Sample clock
timebase VCXO to synchronize to a Reference clock. The frequency
stability of the Sample clock timebase matches that of the PLL
Reference clock when the two are phase-locked. Phase-locking also
synchronizes multiple device clocks that are phase–locked to the same
Reference clock.
Channel
Delay
Divide/N
Sample
Channel
Clock
Delay
Timebase
2-35
Chapter 2
NI 5450 Overview
Reference Clock
Sample Clock
Timebase/M
Divide/M
Divide/K
CH 0
Sample Clock
CH 1
Sample Clock
NI PXIe-5450 User Manual
CLK OUT
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