Motorola ASTRO XTL 5000 Basic Service Manual page 48

3-26
3.12 UHF Receiver Overview
The primary duties of the UHF receiver circuits are to detect, filter, amplify, and demodulate RF
signals in the presence of strong interfering noise and unintended signals. The receiver contains the
following blocks:
• Front-end (preselectors and LNAs)
• Mixer
• IF
• Back-end
3.12.1 Receiver Front-End
The UHF receiver operates in the frequency range of 380 to 470 MHz for Range 1 and 450 to
520 MHz for Range 2. The primary function of the receiver front-end is to optimize the rejection of
the image frequency and other out-of-band frequencies while providing low-noise amplification of the
received signal. The front-end uses a discrete bipolar LNA, a discrete varactor-tuned filter, a
microwave monolithic IC (MMIC) LNA, and a discrete fixed-tuned image filter. The front-end has two
possible configurations: standard mode, which provides the best intermodulation performance, and
the optional pre-amplifier mode, which provides improved sensitivity at the cost of slightly reduced
intermodulation performance. The front-end lineup for standard mode is a varactor-tuned filter, MMIC
LNA, and image filter. In pre-amp mode, an additional LNA is added by means of discrete PIN diode
switches.
3.12.2 Mixer
The receiver front-end signal is fed into a discrete double-balance mixer, where it is down-converted
into an intermediate frequency (IF) of 109.65 MHz. The mixer consists of two balun transformers and
a diode ring. This configuration allows high-level local oscillator (LO) injection, thus maximizing
intermodulation performance. The mixer is driven by the receiver injection buffer, which consists of a
two-stage LDMOS amplifier designed to provide a stable injection level of +23 dBm. The synthesizer
performs high-side injection to the mixer.
3.12.3 IF Circuitry
The crystal filters provide intermediate frequency selectivity and out-of-band signal protection to the
back-end IC. The use of two 2-pole crystal filters centered at 109.65 MHz, which are isolated from
one another by a discrete IF amplifier, enable the receiver to meet specifications for gain, close-in
intermodulation rejection, adjacent channel selectivity and second-image rejection.
3.12.4 Receiver Back-End
The output of the IF circuit is fed directly to the back-end receiver IC. This IC uses a variable-
bandwidth bandpass sigma-delta architecture. It is capable of down-converting analog, as well as
digital, RF protocols into a baseband signal, which is then transmitted over the Synchronous Serial
Interface (SSI) bus. It also converts the 109.65 MHz signal from the IF section down to 2.25 MHz
using a second LO frequency, which is produced by the second LO VCO. This VCO runs at 107.4
(low-side injection) or 111.9 MHz (high-side injection). The choice of frequency depends on known
spurious interference related to the programmed received frequency. The default is low-side
injection.
October 30, 2006
Basic Theory of Operation: UHF Receiver Overview
6871769L01-A