Epson S5U13706B00C User Manual page 8

Installation and Configuration
S1D13706
Switch
Signal
SW1-[3:1] CNF[2:0]
SW1-4 CNF3
SW1-5 CNF4
SW1-6 CNF5
SW1-[8:7] CNF[7:6]
1
SW1-9 -
SW1-10 -
= Required settings when used with PCI Bridge FPGA
8
The S1D13706 has 8 configuration inputs (CONF[7:0]) which are read on the rising edge
of RESET#. All S1D13706 configuration inputs are fully configurable using a ten position
DIP switch as described below.
Table 3-1: Configuration DIP Switch Settings
Value on this pin at rising edge of RESET# is used to configure:
Closed (On/1)
Select host bus interface as follows:
CNF2 CNF1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note: The host bus interface is 16-bit.
Enable GPIO pins
Big Endian bus interface
WAIT# is active high
CLKI to BClk divide select:
CNF7 CNF6
0 0
0 1
1 0
1 1
Hardware Video Invert - invert video data
Disable FPGA for non-PCI host
Note
1
To enable the Hardware Video Invert function the following are required:
• GPIO pins must be enabled (S1-4 closed).
• GPIO0 must be connected to S1-9 (Jumper JP1 set to 1-2).
• GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1.
• GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0.
• Hardware Video Invert Enable bit (REG[70h] bit 5) must be set to 1.
Seiko Epson Corporation
CNF0 Host Bus Interface
0 SH-4/SH-3
1 MC68K #1
0 MC68K #2
1 Generic #1
0 Generic #2
1 RedCap 2
0 DragonBall
1 Reserved
Enable additional pins for D-TFD/HR-TFT
Little Endian bus interface
WAIT# is active low
CLKI to BClk Divide Ratio
1 : 1
2 : 1
3 : 1
4 : 1
1
Hardware Video Invert - normal video data
Enable FPGA for PCI host
Open (Off/0)
S5U13706B00C Rev. 1.0 Evaluation Board
1
Rev. 5.1