Infineon Technologies Cypress CYTVII-B-H-8M-176-CPU User Manual
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Infineon Technologies Cypress CYTVII-B-H-8M-176-CPU User Manual

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Summary of Contents for Infineon Technologies Cypress CYTVII-B-H-8M-176-CPU

  • Page 1 Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
  • Page 2 CYTVII-B-H-8M-176-CPU Evaluation Board User Guide Document Number: 002-25907 Rev. *A Cypress Semiconductor An Infineon Technologies Company 198 Champion Court San Jose, CA 95134-1709 www.cypress.com, www.infineon.com...
  • Page 3 Copyrights © Cypress Semiconductor Corporation, 2019-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.

  • Page 4: Table Of Contents

    Contents 1. Introduction Precautions and Warnings...................4 2. Overview Functional Overview ....................7 3. Operation 4. Connections and Settings Evaluation Board Connections ..................16 Power Supply Settings....................22 External Power Supply Control Signals Settings ............23 Ethernet Settings .......................23 Settings........................24 5. Power Management IC (PMIC) Power Management IC (PMIC) Module ..............25 A.

  • Page 5: Introduction

    Introduction This user guide provides instructions to handle the CYTVII-B-H-8M-176-CPU and CYTVII-B-H-176-SO evaluation boards, collectively referred to as 'CPU board' in this document. This is an evaluation platform for the CYT4BF8C Traveo™ II device. The board can be used as a standalone for basic validation or in combination with the CYTVII-B-E-BB Traveo II base board (available separately from Cypress).

  • Page 6: Overview

    Overview Figure 2-1 shows the CYTVII-B-H-176-SO board. Insert a Traveo II device into the IC socket (highlighted in red) while the evaluation board is powered OFF. Figure 2-1. CYTVII-B-H-176-SO Board A variant of the CPU board (CYTVII-B-H-8M-176-CPU) is also available, where the Traveo II device is soldered directly onto the PCB.
  • Page 7 Overview Figure 2-2. Traveo II Base Board (CYTVII-B-E-BB) Two Samtec connectors on the CPU board and corresponding mating connectors on the base board are used to connect sig- nals across the two boards. When put together, the boards appear as shown in Figure 2-3.

  • Page 8: Functional Overview

    Overview Functional Overview The CPU board has the following components: 1. One Traveo II device, either soldered or mounted on a socket (U3). 2. PMIC to generate the 5-V, 3.3-V, and 1.1-V output, which powers the CPU board and the base board (if connected). ®...
  • Page 9 Overview 2.1.1 Block Diagram The Block Diagram is shown in Figure 2-4. Figure 2-4. Block Diagram Traveo II CYTVII-B-H-8M-176pin CPU Board D-sub Base Board 9 Pin Automotive Ethernet S6BP501A, S6BP502A (PMIC) eMMC Dual Quad Connector SPI Flash Pass Transistor SMIF HyperFlash HyperRAM Traveo II...
  • Page 10 Overview 2.1.2 USB Connector The location of the USB Connector is shown in Figure 2-5. Figure 2-5. USB Connector CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...
  • Page 11 Overview 2.1.3 Ethernet Connector The location of the Ethernet Connector is shown in Figure 2-6. Figure 2-6. Ethernet Connector CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...
  • Page 12 Overview 2.1.4 SMIF Connector The location of the SMIF Connector is shown in Figure 2-7. Figure 2-7. SMIF Connector CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...
  • Page 13 Overview 2.1.5 eMMC Connector The location of the eMMC Connector is shown in Figure 2-8. Figure 2-8. eMMC Connector CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...
  • Page 14 Overview 2.1.6 Audio Connector The location of the Audio Connector is shown in Figure 2-9. Figure 2-9. Audio Connector CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...

  • Page 15: Operation

    Operation This section describes the operation of the CPU board and the base board. It is assumed that you have connected the CPU board to the base board using the Samtec interface and inserted a Traveo II device into the IC socket (applicable to CYTVII- B-H-176-SO boards only).
  • Page 16 Operation Cortex DEBUG and ETM on J22  8. Install the appropriate programming integrated design environment (IDE) on a PC. The programming IDE (GHS MULTI, IAR Embedded Workbench, Cypress Programmer, and so on) should be able to detect a device (read the device ID) and to load a firmware HEX file (.srec) into the device flash successfully.

  • Page 17: Connections And Settings

    Connections and Settings Evaluation Board Connections 4.1.1 Base Board Connections Make sure that the following jumpers are inserted on the base board, so that each transceiver on the base board can be used with the respective firmware example that activate each functionality of the device: CAN0.0 from the device uses the CAN0 transceiver on the base board (connect jumpers J70, J71, J72).
  • Page 18 Connections and Settings Table 4-1. Device Port Pin Connections on Base Board Connection 1 Connection 1 Connection 1 MCU Port Pin CPU Board Base Board Signal Name of Schematics Test Point Test Point VSSD Not applicable P0.0 ETH_REFCLK TP110 Not applicable P0.1 ETH_TXEN TP111...
  • Page 19 Connections and Settings Table 4-1. Device Port Pin Connections on Base Board Connection 1 Connection 1 Connection 1 MCU Port Pin CPU Board Base Board Signal Name of Schematics Test Point Test Point VDDIO_1 Not applicable TP10 Not applicable VSSD Not applicable VCCD Not applicable...
  • Page 20 Connections and Settings Table 4-1. Device Port Pin Connections on Base Board Connection 1 Connection 1 Connection 1 MCU Port Pin CPU Board Base Board Signal Name of Schematics Test Point Test Point VSSD Not applicable P13.0 UART_RX TP185 JP10.4 P13.1 UART_TX TP186...
  • Page 21 Connections and Settings Table 4-1. Device Port Pin Connections on Base Board Connection 1 Connection 1 Connection 1 MCU Port Pin CPU Board Base Board Signal Name of Schematics Test Point Test Point P19.0 GPIO_P19_0 J36.3 Not applicable P19.1 GPIO_P19_1 J37.3 Not applicable P19.2...
  • Page 22 Connections and Settings For each pin, the connected peripheral or net on the base board is depicted by the Netname of Schematics column. The Base Board Test Point column indicates the place where the signal can be probed on the base board. For example, JP6.15 refers to the 15 pin on the JP6 header.

  • Page 23: Power Supply Settings

    Connections and Settings 4.1.6 JTAG Select Jumpers The correspondence between the JTAG Select Jumpers and selected functions is given in Table 4-6. Table 4-6. JTAG Select Jumpers Jumpers Name Part No. Connection Function 1-2 (default) SWJ_TRSTN TRSTN GPIO_P19_0 1-2 (default) SWJ_SWO_TDO SWO_TDO GPIO_P19_1...

  • Page 24: External Power Supply Control Signals Settings

    Connections and Settings Figure 4-1. Power Supply Jumpers Settings VCC11_TR VCC11 VCC11_OUT CPU_VCCD VCC3 VDDD VCC5 CPU_VDDD VDDIO_1 CPU_VDDIO_1 VDDIO_2 CPU_VDDIO_2 CPU_VDDA External Power Supply Control Signals Settings Jumper Settings of the External Power Supply Control Signals from MCU are shown in Table 4-8.

  • Page 25: Settings

    Connections and Settings Settings Settings are shown in Table 4-10. Table 4-10. Settings Function Status Jumper Settings Remarks is enabled Closed is disabled Open CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...

  • Page 26: Power Management Ic (Pmic)

    Power Management IC (PMIC) Power Management IC (PMIC) Module 5.1.1 PMIC Module - CYALKIT-A18 CYALKIT-A18 is the PMIC module for the power block of an automotive application with CYT4B Series MCU. The PMIC Module implements the Cypress PMIC S6BP501A and is optimized for power supply of CYT4B Series MCU. 1.1 V output to supply to VCCD of CYT4B Series MCU needs external schottky barrier diode (SBD), output capacitor and constant load cur- rent no less than 20 mA.
  • Page 27 Power Management IC (PMIC) 5.1.2 Input/Output Pin Descriptions Table 5-1. Input/Output Pin Descriptions Connector Symbol Function Description 1, 2 VOUT3V 3.3 V power rail output terminal (0 A - 0.75 A) 3, 4 PGND Ground terminal Mode setting or external clock input terminal SYNC Refer to the S6BP501A datasheet PG1V...

  • Page 28: Schematics Of Cpu Board

    Schematics of CPU Board CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...
  • Page 29 Figure A-1. Schematic (1/27) TVII-B-H-8M 176 CPU BOARD DSUB 9 AUTOMOTIVE ETHERNET TVII-B-H-8M MONZA DUAL eMMC QUAD_SPI CONNECTOR FLASH PASS TRANSISTOR BASE BOARD SMIF HYPER HYPER INTERFACE FLASH SRAM DEBUG RESET USB-UART INTERFACES CONTROLLER I2S AUDIO INTERFACE CYPRESS SEMICONDUCTOR CYPRESS SEMICONDUCTOR CYPRESS SEMICONDUCTOR 3.5MM 198 CHAMPION COURT...
  • Page 30 Figure A-2. Schematic (2/27) 12V POWER INPUT VCC12V_EXT VCC_12V DEFAULT OPEN HDR_1X2 HDR_1X2 HDR_1X2 FUSE_12V ZENER_12V 1.6A B120-13 THRU HOLE 500SSP1S2M2QEA BLM21PG300SH1D CON_PWRJACK3_RAPC722 47uF 100uF_25V SMAJ12CA 5002 MONITOR LED VCC5 PASS TRANSISTOR VCC5 VCC3 VCC5 220E 220E 220E LED3 LED1 LED2 DRV_VOUT_R {4,8}...
  • Page 31 Figure A-3. Schematic (3/27) Power supply VCC5 VCC_12V VIN-1 VOUT5-1 THRU HOLE VIN-2 VOUT5-2 VCC3 VCC11_TR VOUT3-1 THRU HOLE VCC11 VOUT3-2 FB1V_IN FB1V VCC11_OUT VCC11_FL VCC11_PMIC VOUT1-1 THRU HOLE RSX101MM-30TF 3 Pin Jumper {3,8} DRV_VOUT FB1V_IN VOUT1-2 BLM21PG300SH1D DEFAULT 2-3 CLOSE HDR_1X2 THRU HOLE HDR_1X2...
  • Page 32 Figure A-4. Schematic (4/27) {14} SWJ_TRSTN {5,18} ETH_REFCLK P0.0/PWM1_18/PWM1_22_N/TC1_18_TR0/TC1_22_TR1/PWM0_H_0/ETH0_REF_CLK/SCB0_RX/SCB7_SDA/SCB0_MISO/LIN1_RX {5,18} ETH_TXEN P0.1/PWM1_17/PWM1_18_N/TC1_17_TR0/TC1_18_TR1/PWM0_H_0_N/ETH0_TX_CTL/SCB0_TX/SCB7_SCL/SCB0_MOSI/LIN1_TX {5,18} ETH_TXER P0.2/PWM1_14/PWM1_17_N/TC1_14_TR0/TC1_17_TR1/TC0_H_0_TR0/ETH0_TX_ER/SCB0_RTS/SCB0_SCL/SCB0_CLK/SCB4_MISO/LIN1_EN/CAN0_1_TX {5,18} ETH_TXC P0.3/PWM1_13/PWM1_14_N/TC1_13_TR0/TC1_14_TR1/TC0_H_0_TR1/ETH0_TX_CLK/SCB0_CTS/SCB0_SDA/SCB0_SEL0/SCB4_MOSI/CAN0_1_RX {20,28} BB_SPI0_MISO P1.0/PWM1_12/PWM1_13_N/TC1_12_TR0/TC1_13_TR1/PWM1_H_4/SCB0_SCL/SCB0_MISO/SCB4_CLK {20,28} BB_SPI0_MOSI P1.1/PWM1_11/PWM1_12_N/TC1_11_TR0/TC1_12_TR1/PWM1_H_5/SCB0_SDA/SCB0_MOSI/SCB4_SEL0 {20,25} BB_SPI0_CLK P1.2/PWM1_10/PWM1_11_N/TC1_10_TR0/TC1_11_TR1/PWM1_H_6/SCB0_CLK/LIN0_RX/TRIG_IN[0] {20,25} BB_SPI0_SS0 P1.3/PWM1_8/PWM1_10_N/TC1_8_TR0/TC1_10_TR1/PWM1_H_7/SCB0_SEL0/LIN0_TX/TRIG_IN[1] R203 {5,18} ETH_TXD0 P2.0/PWM1_7/PWM1_8_N/TC1_7_TR0/TC1_8_TR1/ETH0_TXD_0/TC1_H_4_TR0/SCB7_RX/SCB0_SEL1/SCB7_MISO/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] {5,18} ETH_TXD1 P2.1/PWM1_6/PWM1_7_N/TC1_6_TR0/TC1_7_TR1/ETH0_TXD_1/TC1_H_5_TR0/SCB7_TX/SCB7_SDA/SCB0_SEL2/SCB7_MOSI/LIN0_TX/CAN0_0_RX/TRIG_IN[3] {5,18} ETH_TXD2 P2.2/PWM1_5/PWM1_6_N/TC1_5_TR0/TC1_6_TR1/ETH0_TXD_2/TC1_H_6_TR0/SCB7_RTS/SCB7_SCL/SCB0_SEL3/SCB7_CLK/LIN0_EN/TRIG_IN[4] {5,18} ETH_TXD3 P2.3/PWM1_4/PWM1_5_N/TC1_4_TR0/TC1_5_TR1/ETH0_TXD_3/TC1_H_7_TR0/SCB7_CTS/SCB7_SEL0/LIN5_RX/TRIG_IN[5]...
  • Page 33 Figure A-5. Schematic (5/27) {21,22,24} SPIHB_CLK P7.0/PWM1_M_4/PWM1_3_N/TC1_M_4_TR0/TC1_3_TR1/PWM0_1/SPIHB_CLK/SDHC_CARD_MECH_WRITE_PROT/SCB5_RX/SCB5_MISO/LIN4_RX/ADC[0]_16 {21,22,24} SPIHB_RWDS P7.1/PWM1_15/PWM1_M_4_N/TC1_15_TR0/TC1_M_4_TR1/SPIHB_RWDS/SDHC_CLK_CARD/SCB5_TX/SCB5_SDA/SCB5_MOSI/LIN4_TX/ADC[0]_17 {21,22,23,24} SPIHB_SEL0 P7.2/PWM1_M_5/PWM1_15_N/TC1_M_5_TR0/TC1_15_TR1/PWM0_1_N/SPIHB_SEL0/SDHC_CARD_CMD/SCB5_RTS/SCB5_SCL/SCB5_CLK/LIN4_EN/ADC[0]_18 {22,23,24} SPIHB_SEL1 P7.3/PWM1_16/PWM1_M_5_N/TC1_16_TR0/TC1_M_5_TR1/TC0_1_TR0/SPIHB_SEL1/SDHC_CARD_IF_PWR_EN/SCB5_CTS/SCB5_SEL0/CAN0_4_TX/ADC[0]_19 {21,22,24} SPIHB_DATA0 P7.4/PWM1_M_6/PWM1_16_N/TC1_M_6_TR0/TC1_16_TR1/TC0_1_TR1/SPIHB_DATA0/SDHC_CARD_DAT_3TO0_0/SCB5_SEL1/CAN0_4_RX/ADC[0]_20 {21,22,24} SPIHB_DATA1 P7.5/PWM1_17/PWM1_M_6_N/TC1_17_TR0/TC1_M_6_TR1/PWM0_H_2/SPIHB_DATA1/SDHC_CARD_DAT_3TO0_1/LIN10_RX/SCB5_SEL2/ADC[0]_21 {6,25} BB_USER_LED0 P7.6/PWM1_M_7/PWM1_17_N/TC1_M_7_TR0/TC1_17_TR1/LIN10_TX/TRIG_IN[16]/ADC[0]_22 {28} BB_USER_LED1 P7.7/PWM1_18/PWM1_M_7_N/TC1_18_TR0/TC1_M_7_TR1/LIN10_EN/TRIG_IN[17]/ADC[0]_23 {21,22,24} SPIHB_DATA2 P8.0/PWM1_19/PWM1_18_N/TC1_19_TR0/TC1_18_TR1/PWM0_H_2_N/SPIHB_DATA2/SDHC_CARD_DAT_3TO0_2/PWM1_H_8/LIN2_RX/CAN0_0_TX {21,22,24} SPIHB_DATA3 P8.1/PWM1_20/PWM1_19_N/TC1_20_TR0/TC1_19_TR1/TC0_H_2_TR0/SPIHB_DATA3/SDHC_CARD_DAT_3TO0_3/PWM1_H_8_N/LIN2_TX/CAN0_0_RX/TRIG_IN[14]/ADC[0]_24 {22,24} SPIHB_DATA4 P8.2/PWM1_21/PWM1_20_N/TC1_21_TR0/TC1_20_TR1/TC0_H_2_TR1/SPIHB_DATA4/SDHC_CARD_DAT_7TO4_0/TC1_H_8_TR0/LIN2_EN/TRIG_IN[15]/ADC[0]_25 {28} BB_USER_LED2 P8.3/PWM1_22/PWM1_21_N/TC1_22_TR0/TC1_21_TR1/TC1_H_8_TR1/LIN16_RX/TRIG_DBG[0]/ADC[0]_26 {28} BB_USER_LED3 P8.4/PWM1_23/PWM1_22_N/TC1_23_TR0/TC1_22_TR1/LIN16_TX/TRIG_DBG[1]/ADC[0]_27...
  • Page 34 Figure A-6. Schematic (6/27) {7,15,28} UART_RX P13.0/PWM1_M_8/PWM1_43_N/TC1_M_8_TR0/TC1_43_TR1/TC0_2_TR0/AUDIOSS2_MCLK/EXT_MUX[2]_0/SCB3_RX/LIN3_RX/SCB3_MISO/ADC[1]_12 {7,15,28} UART_TX P13.1/PWM1_44/PWM1_M_8_N/TC1_44_TR0/TC1_M_8_TR1/PWM0_2_N/AUDIOSS2_TX_SCK/EXT_MUX[2]_1/SCB3_TX/SCB3_SDA/LIN3_TX/SCB3_MOSI/ADC[1]_13 {28} BB_UART0_RTS P13.2/PWM1_M_9/PWM1_44_N/TC1_M_9_TR0/TC1_44_TR1/PWM0_2/AUDIOSS2_TX_WS/EXT_MUX[2]_2/SCB3_RTS/SCB3_SCL/LIN3_EN/SCB3_CLK/ADC[1]_14 {28} BB_UART0_CTS P13.3/PWM1_45/PWM1_M_9_N/TC1_45_TR0/TC1_M_9_TR1/AUDIOSS2_TX_SDO/EXT_MUX[2]_EN/SCB3_CTS/LIN2_RX/SCB3_SEL0/ADC[1]_15 {27} BB_FRA_STBN P13.4/PWM1_M_10/PWM1_45_N/TC1_M_10_TR0/TC1_45_TR1/LIN8_RX/AUDIOSS2_CLK_I2S_IF/PWM1_H_4/LIN2_TX/SCB3_SEL1/ADC[1]_16 {27} BB_FRA_EN P13.5/PWM1_46/PWM1_M_10_N/TC1_46_TR0/TC1_M_10_TR1/LIN8_TX/AUDIOSS2_RX_SCK/PWM1_H_4_N/SCB3_SEL2/ADC[1]_17 {27} BB_FRA_ERRN P13.6/PWM1_M_11/PWM1_46_N/TC1_M_11_TR0/TC1_46_TR1/LIN8_EN/AUDIOSS2_RX_WS/PWM1_H_5/SCB3_SEL3/TRIG_IN[22]/ADC[1]_18 {27} BB_FRA_WAKE P13.7/PWM1_47/PWM1_M_11_N/TC1_47_TR0/TC1_M_11_TR1/AUDIOSS2_RX_SDI/PWM1_H_5_N/TRIG_IN[23]/ADC[1]_19 R214 {20} AUDIOSS_MCLK P14.0/PWM1_48/PWM1_47_N/TC1_48_TR0/TC1_47_TR1/PWM0_M_1/AUDIOSS1_MCLK/PWM1_H_6/SCB2_MISO/SCB2_RX/CAN1_0_TX/ADC[1]_20 2 Pin Jumper {7,20} AUDIOSS_TX_SCK P14.1/PWM1_49/PWM1_48_N/TC1_49_TR0/TC1_48_TR1/PWM0_M_1_N/AUDIOSS1_TX_SCK/PWM1_H_6_N/SCB2_MOSI/SCB2_SDA/SCB2_TX/CAN1_0_RX/ADC[1]_21 {7,20} AUDIOSS_TX_WS P14.2/PWM1_50/PWM1_49_N/TC1_50_TR0/TC1_49_TR1/TC0_M_1_TR0/AUDIOSS1_TX_WS/PWM1_H_7/SCB2_CLK/SCB2_SCL/SCB2_RTS/LIN6_RX/ADC[1]_22 {7,20} AUDIOSS_TX_SDO...
  • Page 35 Figure A-7. Schematic (7/27) {14} GPIO_P19_0 P19.0/PWM1_M_3/PWM1_50_N/TC1_M_3_TR0/TC1_50_TR1/AUDIOSS0_CLK_I2S_IF/TC1_H_0_TR0/SCB2_MISO/SCB2_RX/CAN1_3_TX/FAULT_OUT_2/ADC[2]_24 {14} GPIO_P19_1 P19.1/PWM1_26/PWM1_M_3_N/TC1_26_TR0/TC1_M_3_TR1/AUDIOSS0_RX_SCK/TC1_H_0_TR1/SCB2_MOSI/SCB2_SDA/SCB2_TX/CAN1_3_RX/FAULT_OUT_3/ADC[2]_25 {14} GPIO_P19_2 P19.2/PWM1_27/PWM1_26_N/TC1_27_TR0/TC1_26_TR1/AUDIOSS0_RX_WS/TC1_H_1_TR0/SCB2_CLK/SCB2_SCL/SCB2_RTS/TRIG_IN[28]/ADC[2]_26 {14} GPIO_P19_3 P19.3/PWM1_28/PWM1_27_N/TC1_28_TR0/TC1_27_TR1/AUDIOSS0_RX_SDI/TC1_H_1_TR1/SCB2_SEL0/SCB2_CTS/TRIG_IN[29]/ADC[2]_27 {14} GPIO_P19_4 P19.4/PWM1_29/PWM1_28_N/TC1_29_TR0/TC1_28_TR1/TC1_H_2_TR0/SCB2_SEL1/ADC[2]_28 {27} BB_LIN2_RXD P20.0/PWM1_30/PWM1_29_N/TC1_30_TR0/TC1_29_TR1/TC1_H_2_TR1/SCB2_SEL2/LIN5_RX/ADC[2]_29 {27} BB_LIN2_TXD P20.1/PWM1_49/PWM1_30_N/TC1_49_TR0/TC1_30_TR1/TC1_H_3_TR0/LIN5_TX/ADC[2]_30 {28} BB_LIN2_SLP P20.2/PWM1_48/PWM1_49_N/TC1_48_TR0/TC1_49_TR1/TC1_H_3_TR1/LIN5_EN/ADC[2]_31 {26} BB_CAN5_TXD P20.3/PWM1_47/PWM1_48_N/TC1_47_TR0/TC1_48_TR1/SCB1_RX/SCB1_MISO/CAN1_2_TX {26} BB_CAN5_RXD P20.4/PWM1_46/PWM1_47_N/TC1_46_TR0/TC1_47_TR1/SCB1_TX/SCB1_SDA/SCB1_MOSI/CAN1_2_RX {25} BB_CAN5_S P20.5/PWM1_45/PWM1_46_N/TC1_45_TR0/TC1_46_TR1/SCB1_RTS/SCB1_SCL/SCB1_CLK {8,26} BB_CAN7_TXD P20.6/PWM1_44/PWM1_45_N/TC1_44_TR0/TC1_45_TR1/SCB1_CTS/SCB1_SEL0/CAN1_4_TX {8,26} BB_CAN7_RXD P20.7/PWM1_43/PWM1_44_N/TC1_43_TR0/TC1_44_TR1/SCB1_SEL1/CAN1_4_RX...
  • Page 36 Figure A-8. Schematic (8/27) PROCESSOR POWER DEFAULT CLOSE FB1V {4} HDR_1X2 VCC11 VCCD VSSD THRU HOLE CPU_VCCD VCCD VCCD 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF DEFAULT CLOSE VCCD HDR_1X2 VCCD VSSD THRU HOLE VDDD CPU_VDDD VCCD VSSD DEFAULT 2-3 CLOSE On each VDDD/VSSD VCC3 3 Pin Jumper...
  • Page 37 Figure A-9. Schematic (9/27) Damping resistor, ECO & WCO need to be tuned {10} WCI/BTB {10} ECI/BTB 10pF ECI/BTB {10} CON_MCXJACK5_F {10} WCO/BTB 16.000MHz 32.768KHz 10pF ECO/BTB {10} CPU_WCO_IN {8} {10} WCI/BTB 12pF 12pF {10} WCO/BTB CPU_WCO_OUT {8} {10} ECI/BTB CPU_ECO_IN {8} CPU_ECO_OUT {8} {10}...
  • Page 38 Figure A-10. Schematic (10/27) PUSH BUTTON HIBERNATE WAKEUP VDDD VDDD HDR_1X2 HDR_1X2 GPIO_SW1_R GPIO_SW1 GPIO_HW_R GPIO_HW HIBERNATE_WAKEUP {8} USER_SW1 {5} PTS810 SJG 250 SMTR LFS 0.1uF PTS810 SJG 250 SMTR LFS 0.1uF DEFAULT CLOSE DEFAULT CLOSE Footprint of J5 Should be Footprint of J5 Should be compatible with a 0E compatible with a 0E...
  • Page 39 Figure A-11. Schematic (11/27) VCC11 VCC5 PLACE NEAR SENSE PIN PLACE NEAR VDD PIN RESET CONTROLLER 1000pF 0.1uF VCC5 VDDD RESET_SNS DEFAULT CLOSE HDR_1X2 VCC5 RST_MR RST_SW RST_MR RST_OUT 100E_1% CPU_XRES {8,13,14,18,20,22} RESET LED6 0.1uF SD05C-01FTG TPS3808G01QDBVRQ1 VCC5 RESET_LED 220E 0.1uF CYPRESS SEMICONDUCTOR CYPRESS SEMICONDUCTOR...
  • Page 40 Figure A-12. Schematic (12/27) DEBUG INTERFACE ARM ETM MICTOR VDDD TRACE_CLOCK {8,14} TRACE_CLOCK_R TRCCLK TRACE_DBGACK VDDD DBGRO DBGACK {13} SRST_MICTOR nSRST EXTTRIG TRACE_VTREF {13,14} SWO_TDO VTREF TRACE_RTCK TRACE_VSUPPLY RTCK VSUPPLY TRACE_TCK {13,14} SWCLK_TCLK TRCDAT7 {13,14} SWDIO_TMS TRCDAT6 0.1uF {13,14} SWDOE_TDI TRCDAT5 {13,14} TRSTN...
  • Page 41 Figure A-13. Schematic (13/27) VDDD 0.1uF VDDD VDDD ARM_JTAG_R1 ARM_JTAG_R2 {13,14} TRSTN TRST {13,14} SWDOE_TDI NC/TDI {13,14} SWDIO_TMS SWDIO/TMS TCLK_R 0.1uF SWDIO_TMS {13,14} {13,14} SWCLK_TCLK SWDCLK/TCLK VTref SWDIO/TMS SWCLK_TCLK {13,14} RTCK SWDCLK/TCK {13,14} SWO_TDO SWO_TDO {13,14} SWO/TDO SW0/TDO SWDOE_TDI {13,14} {14} SRST_IDC20 RESET...
  • Page 42 Figure A-14. Schematic (14/27) VCC3 UART TO USB TRANSCEIVER OVERLAP THE VCCIO_USB_5V PADS OF R57 & R48 VCCIO_USB VCC_USB USB_VIN 600E HDR_1X2 4.7uF 0.1uF 0.1uF 4.7uF 10000pF DEFAULT CLOSE USBDM CON_MUSB-B_5_F VBUS USB_RXR USBDM_CONN 0 ohm USBDP {7,28} UART_RX USBDP USBDP_CONN USBDM USBDP...
  • Page 43 Figure A-15. Schematic (15/27) AUTOM0TIVE ETHERNET VCC3 VCC3 0733910060 3V_RSTX AUTO_ETH_RST_N {18} 18pF 18pF TJA_X0 TJA_X0_RC {18} AUTO_ETH_TXC {18} AUTO_ETH_TXEN TXEN ABM8-25.000MHZ-B2-T {18} AUTO_ETH_TXD3 TXD3 {18} AUTO_ETH_TXD2 TXD2 TJA_X1 TJA_X1_RC {18} AUTO_ETH_TXD1 TXD1 {18} AUTO_ETH_TXD0 TXD0 {18} AUTO_ETH_TXER TXER {18} AUTO_ETH_MDIO MDIO {18}...
  • Page 44 Figure A-16. Schematic (16/27) VCC3 AUTOM0TIVE ETHERNET TJA_VDDIO MPZ2012S101ATD25 0.1uF 0.1uF 0.1uF 1000pF VDD(IO) VBat VDD(IO)4 GND2 GND3 TJA_VDDA TPAD VDDA(TX)1 VDDA(TX) MPZ2012S101ATD25 VDDA(1V8) VDDA(3V3) VDDD(1V8) 0.1uF 0.1uF TJA1100 TJA_VDDA_3V3 MPZ2012S101ATD25 0.1uF 0.01uF CYPRESS SEMICONDUCTOR CYPRESS SEMICONDUCTOR CYPRESS SEMICONDUCTOR 198 CHAMPION COURT 198 CHAMPION COURT 198 CHAMPION COURT SAN JOSE, CA 95134...
  • Page 45 Figure A-17. Schematic (17/27) BUS switch with level shifter VCC3 VCC3 HDR_1X2 VCC3 ETH_EN 0.1uF ETH_REFCLK AUTO_ETH_REFCLK {16} AUTO_ETH_TXEN {16} ETH_TXEN AUTO_ETH_TXER {16} ETH_TXER AUTO_ETH_TXC {16} ETH_TXC {8,12,13,14,20,22} CPU_XRES AUTO_ETH_RST_N {16} AUTO_ETH_TXD0 {16} ETH_TXD0 ETH_TXD1 AUTO_ETH_TXD1 {16} AUTO_ETH_TXD2 {16} ETH_TXD2 AUTO_ETH_TXD3 {16} ETH_TXD3 SN74CB3T3384PWR...
  • Page 46 Figure A-18. Schematic (18/27) VCC3 VCC3 VCC18 VCC3 AUDIO_INTERFACE AUDIO_DVDD BLM18PG471SN1 0.1uF 0.1uF VCC3 BLM18PG471SN1 R181 {20} AUDIO_CLK_I2S_IF DVSS DVDD AUDIO_AVDD IOVDD AVDD R127 CODEC_MCLK {20} AUDIO_MCLK MCLK DRVDD AUDIO_HPL {20} AUDIO_SPI_CLK SCLK AUDIO_HPR VCC3 NCP1117DT18T5G VCC18 {20} AUDIO_SPI_MISO MISO {20} AUDIO_SPI_MOSI AUDIO_RESET {20}...
  • Page 47 Figure A-19. Schematic (19/27) BUS switch with level shifter VCC3 VCC3 HDR_1X2 VCC3 AUDIO_EN 0.1uF AUDIOSS_MCLK AUDIO_MCLK {19} AUDIOSS_TX_SCK AUDIO_SCK {19} AUDIOSS_TX_WS AUDIO_WS {19} AUDIOSS_TX_SDO AUDIO_TX_SDO {19} {8,12,13,14,18,22} CPU_XRES AUDIO_RESET {19} AUDIOSS_CLK_I2S_IF AUDIO_CLK_I2S_IF {19} AUDIOSS_RX_SCK AUDIOSS_RX_WS AUDIOSS_RX_SDI AUDIO_RX_SDI {19} SN74CB3T3384PWR BUS switch with level shifter VCC3 VCC3...
  • Page 48 Figure A-20. Schematic (20/27) eMMC_INTERFACE VCC3 VCC3 0.1uF R195 2 Pin Jumper EMMC_WP EMMC_DATA3 {6,22,24} SPIHB_CLK DATA3 EMMC_CMD EMMC_CLK R196 2 Pin Jumper {6,22,24} SPIHB_RWDS R197 2 Pin Jumper EMMC_CMD EMMC_CLK {6,22,23,24} SPIHB_SEL0 EMMC_CD EMMC_DATA0 R198 2 Pin Jumper SDHC_CD DATA0 EMMC_DATA1 DATA1...
  • Page 49 Figure A-21. Schematic (21/27) VCC3 VCC3 VCC3 VCC3 H-FLASH HFLASH_CS0 R155 2 Pin Jumper CS1# SPIHB_SEL0 {6,21,23,24} VCCQ CS2# VCCQ GM_CK HFLASH_RSTO TP22 RSTO# MEM_RSTX GM_DQ0 RESET# HFLASH_INT GM_DQ1 VCC3 TP23 INT# HFLASH_PSC GM_DQ2 TP24 RFU1 GM_RWDS GM_DQ3 RWDS HFLASH_RFU2 GM_DQ4 TP25 RFU2...
  • Page 50 Figure A-22. Schematic (22/27) DUAL QUAD-SPI VCC3 VCC3 VCC3 C100 0.1uF {22} GM_DQ3 GM_CK {22} HOLD#/IO3 GM_DQ0 {22} SI/IO0 {22} MEM_RSTX RESET#/RFU VIO/RFU DNU1 DNU2 DNU3 DNU4 QSPI_CS0 R169 {6,21,22,24} SPIHB_SEL0 {22} GM_DQ1 GM_DQ2 {22} SO/IO1 WP#/IO2 2 Pin Jumper S25FL256SAGMFM000 VCC3 C101...
  • Page 51 Figure A-23. Schematic (23/27) SMIF CONNECTOR VCC3 VCC18 VCC5 VCC5 VCC18 VCC3 GND1 GND2 VDDIO1 VDDIO2 GND3 GND4 R182 SMIF_D0 SMIF_D1 R193 SPIHB_DATA1 {6,21,22} {6,21,22} SPIHB_DATA0 SMIF_D2 SMIF_D3 R183 R192 {6,21,22} SPIHB_DATA2 SPIHB_DATA3 {6,21,22} GND5 GND6 R184 SMIF_D4 SMIF_D5 R191 {6,22} SPIHB_DATA4 SPIHB_DATA5 {6,22}...
  • Page 52 Figure A-24. Schematic (24/27) BOARD TO BOARD CONNECTOR - J34A This connects to J84 J34A on the TVII Base board BB_USER_LED0 {6} BB_SPI0_SS0 {5,20} BB_SPI0_CLK {5,20} GPIO_P6_3 {5} GPIO_P22_3 {8} GPIO_023 TP37 GPIO_024 TP38 BB_UART1_RX TP39 BB_UART1_TX TP40 BB_UART1_RTS TP41 BB_UART1_CTS TP42 BB_CAN2_TXD {6}...
  • Page 53 Figure A-25. Schematic (25/27) BOARD TO BOARD CONNECTOR - J34B BB_P_3V3 VCC3 This connects to J84 on the TVII Base board R175 3216 0ohm Place R81 closer to the Samtec Connector J35 J34B BB_CAN6_TXD BB_CAN6_RXD BB_CAN5_TXD {8} BB_CAN7_TXD BB_CAN5_RXD {8} BB_CAN7_RXD BB_CAN4_TXD {6} BB_CAN4_RXD {6}...
  • Page 54 Figure A-26. Schematic (26/27) BOARD TO BOARD CONNECTOR - J35A BB_P_5V VCC5 This connects to J38 R173 3216 0ohm on the TVII Base board BB_P_5V BB_P_12V BB_P_12V VCC_12V J35A R174 3216 0ohm BB_CAN1_RXD BB_USER_LED8 {6} BB_CAN1_TXD BB_CAN1_S GPIO_P5_4 BB_CAN0_RXD TP99 BB_CAN0_TXD TP100 BB_USER_LED9 {6}...
  • Page 55 Figure A-27. Schematic (27/27) BOARD TO BOARD CONNECTOR - J35B This connects to J38 on the TVII Base board J35B GPIO_074 TP70 BB_LIN2_SLP GPIO_075 TP71 BB_LIN3_RXD GPIO_076 TP72 BB_LIN3_TXD GPIO_077 TP73 BB_LIN3_WAKE GPIO_063 TP74 BB_LIN3_SLP BB_LIN4_RXD GPIO_064 TP75 BB_LIN4_TXD BB_LIN4_WAKE BB_LIN4_SLP BB_ADC_POT {5,20}...

  • Page 56: Component Assembly On Cpu Board

    Component Assembly on CPU Board CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...
  • Page 57 Figure B-1. Component Assembly (Top) CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...
  • Page 58 Figure B-2. Component Assembly (Bottom) CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...

  • Page 59: Schematics Of Base Board

    Schematics of Base Board CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...
  • Page 60 Figure C-1. Schematic (1/16) CYPRESS SEMICONDUCTOR CYPRESS SEMICONDUCTOR CYPRESS SEMICONDUCTOR 198 CHAMPION COURT 198 CHAMPION COURT 198 CHAMPION COURT SAN JOSE, CA 95134 SAN JOSE, CA 95134 SAN JOSE, CA 95134 (408) 943-2600 (408) 943-2600 (408) 943-2600 CYPRESS SEMICONDUCTOR © 2018 CYPRESS SEMICONDUCTOR ©...
  • Page 61 Figure C-2. Schematic (2/16) BTOB CONNECTOR-01 P_3V3 J84A J84B BB_USER_BUTTON_4 16,17 BB_USER_LED0 16,18 CAN6_TXD CAN8_WAKE 9,17 CAN6_RXD SPI0_SS 15,17 CAN9_WAKE 9,17 SPI0_CLK 15,17 CAN5_TXD 7,17 CAN5_RXD 7,17 CAN7_TXD BB_EXP1_GPIO_1 18 CAN7_RXD CAN4_TXD 7,17 BB_EXP1_GPIO_2 18 CAN4_RXD 7,17 BB_EXP1_GPIO_3 18 CAN8_TXD BB_EXP1_GPIO_4 18 CAN8_RXD TP10...
  • Page 62 Figure C-3. Schematic (3/16) BTOB CONNECTOR-02 P_5V P_12V J38A J38B 6,17 CAN1_RXD BB_EXP2_GPIO_6 18 BB_USER_LED8 16,17 11,17 LIN2_SLP 11,17 LIN3_RXD 6,17 CAN1_TXD BB_EXP2_GPIO_1 18 BB_EXP2_GPIO_7 18 6,17 CAN1_S BB_EXP2_GPIO_2 18 11,17 LIN3_TXD BB_EXP2_GPIO_8 18 6,17 CAN0_RXD 11,17 LIN3_WAKE BB_EXP2_GPIO_9 18 BB_EXP2_GPIO_10 18 6,17 CAN0_TXD...
  • Page 63 Figure C-4. Schematic (4/16) CAN_FD_0 CAN_FD_1 VDD_IO VDD_IO CON_DSUB_9_MM CON_DSUB_9_MM HDR_1X2 HDR_1X2 HDR_1X2 HDR_1X2 Default Closed 22uF_20V 0.1uF 22uF_20V 0.1uF Default Closed CAN0_TXD_W CAN0_H_W CAN0_H CAN1_TXD_W CAN1_H_W CAN1_H 5,17 CAN0_TXD 5,17 CAN1_TXD CANH CANH CAN0_RXD_W CAN0_L_W CAN0_L CAN1_RXD_W CAN1_L_W CAN1_L 5,17 CAN0_RXD CANL...
  • Page 64 Figure C-5. Schematic (5/16) CAN_FD_4 CAN_FD_5 VDD_IO VDD_IO CON_DSUB_9_MM CON_DSUB_9_MM HDR_1X2 HDR_1X2 HDR_1X2 HDR_1X2 Default Closed 22uF_20V Default Closed 22uF_20V 0.1uF 0.1uF CAN4_TXD_W CAN4_H_W R117 0E CAN4_H CAN5_TXD_W CAN5_H_W R112 0E CAN5_H 4,17 CAN4_TXD 4,17 CAN5_TXD CANH CANH CAN4_RXD_W CAN4_L_W CAN4_L CAN5_RXD_W CAN5_L_W...
  • Page 65 Figure C-6. Schematic (6/16) CAN_FD_6 CAN_FD_7 VCC_5V VDD_IO VBAT VCC_5V VDD_IO VBAT CON_DSUB_9_MM CON_DSUB_9_MM J109 HDR_1X2 HDR_1X2 HDR_1X2 HDR_1X2 Default Closed Default Closed CAN6_TXD_W CAN6_H_W CAN6_H CAN7_TXD_W CAN7_H_W CAN7_H R126 0E R129 0E CAN6_TXD CAN7_TXD CANH CANH CAN6_RXD_W CAN6_L_W R125 0E CAN6_L CAN7_RXD_W CAN7_L_W...
  • Page 66 Figure C-7. Schematic (7/16) CAN_FD_8 CAN_FD_9 VCC_5V VDD_IO VBAT VCC_5V VDD_IO VBAT CON_DSUB_9_MM CON_DSUB_9_MM J113 J112 J131 J114 HDR_1X2 HDR_1X2 HDR_1X2 HDR_1X2 Default Closed Default Closed CAN8_TXD_W CAN8_H_W CAN8_H CAN9_TXD_W CAN9_H_W CAN9_H R140 0E R137 0E CAN8_TXD CAN9_TXD CANH CANH CAN8_RXD_W CAN8_L_W R139 0E...
  • Page 67 Figure C-8. Schematic (8/16) LIN0_INTERFACE LIN1_INTERFACE HDR_1X2 HDR_1X2 CON_DSUB_9_MM Default Closed Default Closed CON_DSUB_9_MM VBAT VBAT LIN_VS LIN_VS 1N4002-T 1N4002-T LIN0_BUS LIN1_BUS VDD_IO 22uF_20V 22uF_20V 0.1uF VDD_IO 0.1uF Default Open Default Open 4.7K_1% HDR_1X2 HDR_1X2 HDR_1X2 HDR_1X2 4.7K_1% 1N4148W-7-F 1N4148W-7-F Default closed Default closed 1000pF...
  • Page 68 Figure C-9. Schematic (9/16) LIN2_INTERFACE LIN3_INTERFACE HDR_1X2 HDR_1X2 CON_DSUB_9_MM Default Closed CON_DSUB_9_MM VBAT Default Closed VBAT LIN_VS LIN_VS 1N4002-T 1N4002-T LIN2_BUS LIN3_BUS VDD_IO VDD_IO 22uF_20V 22uF_20V 0.1uF 0.1uF Default Open Default Open 4.7K_1% HDR_1X2 HDR_1X2 HDR_1X2 HDR_1X2 4.7K_1% Default closed Default closed 1N4148W-7-F 1N4148W-7-F...
  • Page 69 Figure C-10. Schematic (10/16) LIN4_INTERFACE LIN5_INTERFACE HDR_1X2 HDR_1X2 CON_DSUB_9_MM CON_DSUB_9_MM Default Closed VBAT Default Closed VBAT LIN_VS LIN_VS 1N4002-T 1N4002-T LIN4_BUS LIN5_BUS VDD_IO VDD_IO 22uF_20V 22uF_20V 0.1uF 0.1uF Default Open Default Open HDR_1X2 HDR_1X2 HDR_1X2 HDR_1X2 4.7K_1% 4.7K_1% Default closed Default closed 1N4148W-7-F 1N4148W-7-F...
  • Page 70 Figure C-11. Schematic (11/16) FLEXRAY INTERFACE -01 RESET VDD_IO VDD_IO VBAT Place C67, C68, C69 &C70 close to pin 0.1uF FRA_TXD_W FRA_ERRN_W FRA_TXD FRA_ERRN ERRN FRA_RXD_W CON_DSUB_9_MM FRA_RXD FRA_INH_W FRA_INH FRA_TXEN_W FRA_TXEN TXEN FRA_BP_W RXEN FRA_BM_W FRA_BGE BB_RST_NP RESET FRA_STBN_W FRA_BP FRA_STBN STBN...
  • Page 71 Figure C-12. Schematic (12/16) FLEXRAY INTERFACE-02 SUPPLY_INH HDR_1X2 VDD_IO Default Closed VDD_IO VBAT 4.7K_1% Place C72, C73, C74 & C75 close to pin SUPPLY_INH_W LIN0_INH SUPPLY_INH 5,17 1N4148W-7-F FRB_TXD_W FRB_ERRN_W FRB_TXD FRB_ERRN LIN1_INH ERRN FRB_RXD_W CON_DSUB_9_MM 1N4148W-7-F FRB_RXD FRB_INH_W FRB_INH LIN2_INH FRB_TXEN_W 1N4148W-7-F...
  • Page 72 Figure C-13. Schematic (13/16) HDR_1X2 CXPI_INTERFACE EEPROM INTERFACE Default Closed CXPI_VS VBAT VDD_IO 1N4002-T VDD_IO 22uF_20V 1N4148W-7-F 0.1uF CON_DSUB_9_M HDR_1X2 HDR_1X2 4.7K_1% HDR_1X2 HDR_1X2 HDR_1X2 HDR_1X2 Default Closed Default Closed 10uF 0.1uF Default closed CXPI_TXD_W CXPI_BUS 5,17 CXPI_TXD CXPI_RXD_W SPI0_MOSI_W SPI0_MISO_W 5,18 SPI0_MOSI...
  • Page 73 Figure C-14. Schematic (14/16) USER_LED INTERFACE NOTE: 5-RED & 5-GREEN LED COLOR BB_USER_LED0_W LTST-C150GKT BB_USER_LED4_W LTST-C150GKT 4,18 BB_USER_LED0 5,18 BB_USER_LED4 BB_USER_LED1_W LD10 LTST-C150GKT BB_USER_LED5_W LTST-C150GKT 5,18 BB_USER_LED1 5,18 BB_USER_LED5 BB_USER_LED2_W LD11 LTST-C150GKT BB_USER_LED6_W LTST-C150GKT 5,18 BB_USER_LED2 5,18 BB_USER_LED6 BB_USER_LED3_W LD12 LTST-C150GKT BB_USER_LED7_W LTST-C150GKT...
  • Page 74 Figure C-15. Schematic (15/16) PIN HEADER SECTION -01 VCC_3V3 VCC_5V VCC_3V3 VCC_5V JP10 BB_PWM_2 BB_PWM_1 UART1_RX UART1_TX BB_PWM_4 BB_PWM_3 UART1_CTS UART1_RTS BB_PWM_6 BB_PWM_5 CAN2_RXD CAN2_TXD BB_ADC_2 BB_PWM_7 CAN_SPI1_SS1 CAN_SPI1_SS0 BB_ADC_4 BB_ADC_3 CAN2_S CAN_SPI1_SS2 BB_ADC_6 BB_ADC_5 CAN4_S CAN3_S BB_ADC_8 BB_ADC_7 CAN8_WAKE CAN5_S 4,15 SPI0_CLK...
  • Page 75 Figure C-16. Schematic (16/16) PIN HEADER SECTION -02 VCC_5V VCC_3V3 VCC_5V VCC_3V3 DEBUG_GPIO_5 SPI2_MISO DEBUG_GPIO_6 SPI2_MOSI UART0_RX UART0_CTS DEBUG_GPIO_7 SPI2_CLK UART0_RTS UART0_TX 5 DEBUG_GPIO_8 SPI2_SS 5,16 BB_USER_LED7 BB_USER_LED5 5,16 DEBUG_GPIO_9 CAN3_TXD DEBUG_GPIO_10 CAN3_RXD 5,16 BB_USER_LED3 BB_USER_LED1 5,16 5,15 BB_ADC_POT BB_ADC_1 DEBUG_GPIO_11 SPI0_MOSI 5,15...

  • Page 76: Component Assembly On Base Board

    Component Assembly on Base Board CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...
  • Page 77 Figure D-1. Component Assembly (Top) CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...
  • Page 78 Figure D-2. Component Assembly (Bottom) CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...

  • Page 79: Revision History

    Revision History Document Revision History Document Title: CYTVII-B-H-8M-176-CPU Evaluation Board User Guide Document Number: 002-25907 Revision ECN# Issue Date Description of Change 6493098 02/25/2019 New User Guide 6923377 07/15/2020 Added content under Figure 2-1 CYTVII-B-H-1M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *A...

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