Cpu 3/7 (Ddr3; Cpu 4/7 (Power - Clevo B5130M Service Manual

CPU 4/7 (Power)

PR OCESS OR
U 4 0 F
PROCE SSOR CORE P OWER
V C OR E
52A
A G 35
V C C 1
A G 34
I CC MA X M a xi mu m P ro c es so r S V 5 2
V C C 2
A G 33
A G 32 V C C 3
C or e I CC X E 6 5
V C C 4
A G 31
V C C 5
V C O R E A G 30
V C C 6
A G 29
A G 28 V C C 7
C 1 5 0 C 1 5 7 C 1 6 5 C 1 73
V C C 8
A G 27
V C C 9
A G 26
V C C 1 0
A F 35
A F 34 V C C 1 1
V C C 1 2
A F 33
V C C 1 3
A F 32
V C C 1 4
A F 31
A F 30 V C C 1 5
V C C 1 6
A F 29
V C C 1 7
A F 28
A F 27 V C C 1 8
V C C 1 9
A F 26
V C C 2 0
A D 35
V C C 2 1
C 1 4 5 C 1 7 1 C 1 6 3 C 1 83 A D 34
A D 33 V C C 2 2
V C C 2 3
A D 32
V C C 2 4
A D 31
V C C 2 5
A D 30
A D 29 V C C 2 6
V C C 2 7
A D 28
V C C 2 8
A D 27
V C C 2 9
A D 26
A C 35 V C C 3 0
V C C 3 1
A C 34
V C C 3 2
A C 33
V C C 3 3
A C 32
V C C 3 4
A C 31
V C C 3 5
A C 30
C 5 8 4 C 1 4 4 C 1 4 9 C 1 56
V C C 3 6
A C 29
A C 28 V C C 3 7
V C C 3 8
A C 27
V C C 3 9
A C 26
V C C 4 0
A A 35
A A 34 V C C 4 1
V C C 4 2
A A 33
V C C 4 3
A A 32
V C C 4 4
A A 31
A A 30 V C C 4 5
V C C 4 6
A A 29
V C C 4 7
A A 28
V C C 4 8
A A 27
A A 26 V C C 4 9
V C C 5 0
Y 35
V C C 5 1
Y 34
Y 33 V C C 5 2
V C C 5 3
V C O R E Y 32
V C C 5 4
Y 31
V C C 5 5
C 5 7 3 C 5 6 9 C 5 6 5 C 5 6 4 Y 30
Y 29 V C C 5 6
V C C 5 7
Y 28
V C C 5 8
Y 27
V C C 5 9
Y 26
V 35 V C C 6 0
V C C 6 1
V 34
V C C 6 2
V 33
V C C 6 3
V 32
V 31 V C C 6 4
V C C 6 5
V 30
V C C 6 6
V 29
V 28 V C C 6 7
C 5 7 0 C 5 7 4 C 5 8 0 C 5 60
V C C 6 8
V 27
V C C 6 9
V 26
V C C 7 0
U 35
U 34 V C C 7 1
V C C 7 2
U 33
V C C 7 3
U 32
V C C 7 4
U 31
U 30 V C C 7 5
V C C 7 6
U 29
U 28 V C C 7 7
V C C 7 8
U 27
U 26 V C C 7 9
C 5 7 9 C 5 6 6 C 5 6 3 C 5 59
V C C 8 0
R 35
V C C 8 1
R 34
R 33 V C C 8 2
V C C 8 3
R 32
V C C 8 4
R 31
V C C 8 5
R 30
R 29 V C C 8 6
V C C 8 7
R 28
V C C 8 8
R 27
V C C 8 9
R 26
P 35 V C C 9 0
V C C 9 1
P 34
V C C 9 2
P 33
V C C 9 3
P 32
P 31 V C C 9 4
V C C 9 5
P 30
V C C 9 6
P 29
V C C 9 7
P 28
V C C 9 8
P 27
V C C 9 9
P 26
V C C 1 0 0
P Z 9 8 9 2 7 -3 64 1 -0 1 F
4 /7 ( POWE R )
PROCESSOR UNCORE POWE R
A H 1 4
V T T 0 _ 1
A H 1 2
V T T 0 _ 2
A H 1 1 C 17 7 C 18 6 C 1 70
V T T 0 _ 3 A H 1 0
V T T 0 _ 4
J 1 4
1 0 u _6 . 3 V _ X 5 R _ 06 1 0 u _ 6. 3 V _X 5 R _ 06
V T T 0 _ 5
J 1 3
1 0 u _6 . 3 V _X 5 R _ 06
V T T 0 _ 6
H 14
V T T 0 _ 7 H 12
V T T 0 _ 8
G 14
V T T 0 _ 9
G 13
V T T 0 _ 1 0
G 12
V T T 0 _ 1 1 G 11
V T T 0 _ 1 2
F 1 4
C 18 0 C 17 9 C 1 74
V T T 0 _ 1 3
F 1 3
V T T 0 _ 1 4
F 1 2 1 0 u _6 . 3 V _ X 5 R _ 06 1 0 u _ 6. 3 V _X 5 R _ 06
V T T 0 _ 1 5 F 1 1
1 0 u _6 . 3 V _X 5 R _ 06
V T T 0 _ 1 6
E 1 4
V T T 0 _ 1 7
E 1 2
V T T 0 _ 1 8 D 14
V T T 0 _ 1 9
D 13
V T T 0 _ 2 0
D 12
V T T 0 _ 2 1
D 11
V T T 0 _ 2 2 C 14
V T T 0 _ 2 3
C 13
V T T 0 _ 2 4
C 12
V T T 0 _ 2 5
C 11
V T T 0 _ 2 6 B 1 4
V T T 0 _ 2 7
B 1 2
V T T 0 _ 2 8
A 1 4
V T T 0 _ 2 9
A 1 3
V T T 0 _ 3 0 A 1 2
V T T 0 _ 3 1
A 1 1
V T T 0 _ 3 2
A F 1 0
V T T 0 _ 3 3
A E 1 0
V T T 0 _ 3 4 A C 1 0
C 18 7 C 1 88
V T T 0 _ 3 5
A B 1 0
V T T 0 _ 3 6
Y 10
2 2 u _6 . 3 V _ X 5 R _ 08 2 2 u _ 6. 3V _ X5 R _ 0 8
V T T 0 _ 3 7
W 1 0
V T T 0 _ 3 8 U 10
V T T 0 _ 3 9
T 1 0
V T T 0 _ 4 0
J 1 2
V T T 0 _ 4 1
J 1 1
V T T 0 _ 4 2 J 1 6 + V T T _ 4 3 R 4 34 *1 0 m i l _ s h o r t
V T T 0 _ 4 3
J 1 5 + V T T _ 4 4
R 4 35 *1 0 m i l _ s h o r t
V T T 0 _ 4 4
1 . 1 V S _ V T T
1 K P U t o V TT a n d 1K PD t o G ND
f o r P OC
VCORE
A N 3 3
P S I #
P S I #
A K 3 5
H _ V I D 0 4 3
V I D [ 0] A K 3 3
V I D [ 1] H _ V I D 1 4 3
A K 3 4
V I D [ 2] H _ V I D 2 4 3
A L 3 5
H _ V I D 3 4 3
V I D [ 3] A L 3 3
V I D [ 4] H _ V I D 4 4 3
A M 3 3
V I D [ 5] H _ V I D 5 4 3
A M 3 5
V I D [ 6] H _ V I D 6 4 3
A M 3 4
P R OC _ D P R S LP V R
G 15
H _ V TT V I D 1 4 1
V T T _S E L E C T
TO VCORE POWER C ONTROL
A N 3 5
I M ON 4 3
I S E N S E
A J 3 4
V C C _ S E N S E 4 3
V C C _ S E N S E
A J 3 5
V S S _S E N S E 4 3
V S S _ S E N S E
B 1 5
V T T _ S E N S E 4 1 , 4 2
V T T _ S E N S E
A 1 5
V S S _ S E N S E _ V T T
1 . 1 V S _V T T
VTT T OTAL 21A
C 1 90 C 2 0 4 C 1 7 5 C 5 8 5
* 1 0U _ 6 . 3 V _ 0 6 2 2 u _ 6 . 3 V _ X 5R _ 0 8 22 u _ 6 . 3 V _ X 5 R _ 0 8
* 10 U _ 6 . 3 V _ 0 6
C 6 26 I CC MAX _V TT Ma x C ur ren t
f or VT T Rai l
1 0 u _ 6. 3V _ X5 R _ 0 6
SV 1 8
XE 2 1
The decoupling capacitors, filter
recommendations and sense resistors on the
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
1 . 1 V S _ V TT
Design Guide
C 5 8 6
2 2 u _ 6 . 3 V _ X 5 R _ 0 8
1.1VS_VTT
Please note that the
VTT Rail Val ues are
Auburndale V TT=1.05V
Clarksfield VTT=1.1V
R 1 04
* 1K _ 04
P S I # 43
1 . 1 V S _ V T T
R 1 05
1 K _ 0 4
R 7 0
1 K _ 0 4
P M _D P R S L P V R 4 3
V C O R E 4 3
1 . 1 V S _V TT 2, 4, 7, 1 9 , 2 0 , 2 1 , 2 4 , 2 5 , 2 6, 39 , 4 1 , 4 2 , 4 3
Schematic Diagrams
Sheet 6 of 53
CPU 4/7
(Power)
CPU 4/7 (Power) B - 7