Cpu 6/7 (Gnd - Clevo B5130M Service Manual

Schematic Diagrams
CPU 7/7 (RESERVED)
PCI-Express Co nfiguration Select
CFG0
CFG3 - PCI-Exp ress Static Lane Re versal
Sheet 9 of 53
CFG3
CPU 7/7
(RESERVED)
CFG4 - Display Port Presence
CFG4
CFG7
Clarksfield (only for early samples
pre-ES1) - Connect to GND with 3.01K Ohm/5%
resistor
B - 10 CPU 7/7 (RESERVED)
1 0 MV R E F _D Q _D IM 0
1 : Single PEG
0 : Bifurc ation enable
4 DR A M R S T _ C NT R L
C F G 0 R 1 0 6 * 3. 01 k _ 0 4
11 M V R E F _ D Q_ D IM1
1 : Normal Operation
0 : Lane N umbers Reversed
15 -> 0, 1 4 -> 1, ...
4 DR A M R S T _ C NT R L
C F G 3 R 6 1 * 3. 01 k _ 0 4
1 : Disablled; No physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port
device is connected to the Embedded
isplay Port
C F G 4 R 1 0 2 * 3. 01 k _ 0 4
C F G 7
R 6 2 * 3. 01 k _ 0 4
PROCESSOR 7/7 ( RESERVED )
U 40 E
R 2 3 8 0 _ 0 4
A P 2 5
A L 2 5 RS V D1
RS V D2
D S A L 2 4
V RE F _ CH _ A _ DI M M
RS V D3
A L 2 2
RS V D4
Q 30 A J 3 3
A G 9 RS V D5
* A O3 4 0 2 L R2 3 3
RS V D6
M 2 7
RS V D7
*1 0 0 K _ 04 L 2 8
J 1 7 RS V D8
RS V D9
H 1 7
RS V D1 0
G 2 5
G 1 7 RS V D1 1
R2 4 9 0 _ 0 4
RS V D1 2
E 3 1
RS V D1 3
E 3 0
RS V D1 4
D S
V RE F _ CH _ B _ DI M M V RE F _ CH _ B _ DI M M
Q 31
* A O3 4 0 2 L R2 4 2
*1 0 0 K _ 04
A M 3 0
C F G0
CF G[0 ]
A M 2 8
CF G[1 ]
A P 3 1
A L 3 2 CF G[2 ]
C F G3
CF G[3 ]
C F G4 A L 3 0
CF G[4 ]
A M 3 1
A N 2 9 CF G[5 ]
CF G[6 ]
A M 3 2
C F G7
CF G[7 ]
A K 3 2
CF G[8 ]
A K 3 1
A K 2 8 CF G[9 ]
CF G[1 0 ]
A J 2 8
CF G[1 1 ]
A N 3 0
A N 3 2 CF G[1 2 ]
CF G[1 3 ]
A J 3 2
CF G[1 4 ]
A J 2 9
A J 3 0 CF G[1 5 ]
CF G[1 6 ]
A K 3 0
CF G[1 7 ]
R S V D 8 6 H 1 6
R 4 32 *0 _ 0 4
RS V D_ T P _ 8 6
RSVD 86
Conn ect to GND
B 1 9
RS V D1 5
A 1 9
RS V D1 6
A 2 0
R 4 30 * 1 0m i l _ s ho rt H _ R S V D 1 7 _R
RS V D1 7
H _ R S V D 1 8 _R B 2 0
R 4 31 * 1 0m i l _ s ho rt
RS V D1 8
U 9
RS V D1 9
T 9
RS V D2 0
A C 9
RS V D2 1
A B 9
RS V D2 2
C 1
RS V D_ N CT F _ 2 3
A 3
RS V D_ N CT F _ 2 4
J 2 9
RS V D2 6
J 2 8
RS V D2 7
A 3 4
RS V D_ N CT F _ 2 8
A 3 3
RS V D_ N CT F _ 2 9
C 3 5
RS V D_ N CT F _ 3 0
B 3 5
RS V D_ N CT F _ 3 1
P Z 9 8 9 2 7 -3 64 1 -0 1 F
A J1 3
R S V D3 2 A J1 2
R S V D3 3
A H2 5
R S V D3 4
A K 2 6
R S V D3 5
A L2 6
R S V D3 6 A R2
R S V D_ N CT F _ 3 7
A J2 6
R S V D3 8 A J2 7
R S V D3 9
A P 1
R S V D_ N CT F _ 4 0
A T2
R S V D_ N CT F _ 4 1
A T3
R S V D_ N CT F _ 4 2
A R1
R S V D_ N CT F _ 4 3
A L2 8
R S V D4 5 A L2 9
R S V D4 6
A P 3 0
R S V D4 7
A P 3 2
R S V D4 8 A L2 7
R S V D4 9
A T3 1
R S V D5 0
A T3 2
R S V D5 1 A P 3 3
R S V D5 2
A R3 3
R S V D5 3
A T3 3
R S V D_ N CT F _ 5 4
A T3 4
R S V D_ N CT F _ 5 5 A P 3 5
R S V D_ N CT F _ 5 6
A R3 5
R S V D_ N CT F _ 5 7
A R3 2
R S V D5 8
E 15
R S V D _T P _ 5 9 F 15
R S V D _T P _ 6 0
A 2
K E Y
D 1 5
R S V D6 2 C 1 5
R S V D6 3
A J1 5
R S V D 64 _ R R 1 22 * 1 0m i l _ sh o rt
R S V D6 4
A H1 5 R S V D 65 _ R
R 1 54 * 1 0m i l _ sh o rt
R S V D6 5
A A 5
R S V D _T P _ 6 6 A A 4
R S V D _T P _ 6 7
R 8
R S V D _T P _ 6 8
A D3
R S V D _T P _ 6 9 A D2
R S V D _T P _ 7 0
A A 2
R S V D _T P _ 7 1
A A 1
R S V D _T P _ 7 2
R 9
R S V D _T P _ 7 3 A G7
R S V D _T P _ 7 4
A E 3
R S V D _T P _ 7 5
V 4
R S V D _T P _ 7 6
V 5
R S V D _T P _ 7 7 N 2
R S V D _T P _ 7 8
A D5
R S V D _T P _ 7 9
A D7
R S V D _T P _ 8 0 W 3
R S V D _T P _ 8 1
W 2
R S V D _T P _ 8 2
N 3
R S V D _T P _ 8 3
A E 5
R S V D _T P _ 8 4
A D9
R S V D _T P _ 8 5
A P 3 4
T P _ RS V D8 6
VSS (AP34) can be left NC is
V S S
CRB implementation ; EDS/DG
recommendation to GND