Table of Contents
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User's Guide
AM64x GP EVM User's Guide
1
Introduction.............................................................................................................................................................................3
Notes...........................................................................................................................................................4
2.1 Power-On Usage Note.......................................................................................................................................................
3 System Description................................................................................................................................................................
Features......................................................................................................................................................................5
3.2 Functional Block Diagram..................................................................................................................................................
3.3 Power-On/Off Procedures..................................................................................................................................................
Procedure...................................................................................................................................................8
3.3.2 Power-Off Procedure...................................................................................................................................................
3.4 Peripheral and Major Component Description.................................................................................................................
3.4.1
Clocking.....................................................................................................................................................................10
3.4.1.1 Ethernet PHY Clock............................................................................................................................................
Clock...............................................................................................................................................10
3.4.1.3 PCIe Clock..........................................................................................................................................................
3.4.2
Reset..........................................................................................................................................................................11
3.4.3 Power........................................................................................................................................................................
Input.........................................................................................................................................................12
3.4.3.2 Reverse Polarity Protection................................................................................................................................
3.4.3.3 Current Monitoring..............................................................................................................................................
Supply......................................................................................................................................................13
Sequencing..............................................................................................................................................15
Power..........................................................................................................................................................16
3.4.4 Configuration.............................................................................................................................................................
Modes.........................................................................................................................................................17
3.4.5
JTAG..........................................................................................................................................................................21
Automation.........................................................................................................................................................23
3.4.7 UART Interface..........................................................................................................................................................
Interfaces.....................................................................................................................................................27
3.4.8.1 DDR4 Interface...................................................................................................................................................
3.4.8.2 MMC Interface....................................................................................................................................................
3.4.8.3 OSPI Interface....................................................................................................................................................
3.4.8.5 Board ID EEPROM Interface..............................................................................................................................
3.4.9 Ethernet Interface......................................................................................................................................................
LEDs.....................................................................................................................................................39
Interface......................................................................................................................................................40
Interface.....................................................................................................................................................41
Interface..........................................................................................................................................................41
3.4.13 High Speed Expansion Interface.............................................................................................................................
3.4.14 CAN Interface..........................................................................................................................................................
3.4.15 Interrupt...................................................................................................................................................................
3.4.16 ADC Interface..........................................................................................................................................................
Connector.....................................................................................................................................................49
Interface............................................................................................................................................................49
3.4.19 I2C Interface............................................................................................................................................................
3.4.20 FSI Interface............................................................................................................................................................
4 Known Issues and Modifications........................................................................................................................................
4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS................................................................................
4.2 Issue 2 - MDIO Ethernet PHY Communications..............................................................................................................
SPRUIX0B - FEBRUARY 2021 - REVISED MARCH 2021
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Table of Contents
Interface.......................................................................................................................................30
Configuration..................................................................................................................33
Configuration..................................................................................................................33
Copyright © 2021 Texas Instruments Incorporated
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AM64x GP EVM User's Guide
1
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Summary of Contents for Texas Instruments AM64 GP EVM Series
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Page 1: Table Of Contents
4.1 Issue 1 - Embedded XDS110 Connection to AM64x Target in CCS................4.2 Issue 2 - MDIO Ethernet PHY Communications......................SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... - Page 2 Table 3-21. Display Connector (J36) Pin-Out..........................Table 3-22. PCIe Jumper Options to Enable Root Complex and Endpoint Mode..............AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated...
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Page 3: Introduction
Code Composer Studio ™ , from TI. SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 4: Important Usage Notes
Figure 3-2 for reference to major IC and connector component locations. Figure 3-1. Top View of General Processor Board AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 5: Key Features
1 Mbit Inter-Integrated Circuit (I2C) Boot EEPROM I/O Interface: • One CPSW Gigabit Ethernet port and two Industrial Ethernet ports based on the Gigabit Industrial Communication Subsystem (PRU-ICSS-Gb) paired with Texas Instruments Gigabit Ethernet PHY • One USB2.0 interface with Micro AB connector Expansion Bus: •... - Page 6 Status Output: LEDs to indicate power status • INA devices for current monitoring Compliance: • RoHS Compliant • REACH Compliant AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated...
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Page 7: Functional Block Diagram
AM64x GP EVM. Figure 3-3. General Processor Board Functional Block Diagram SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 8: Power-On/Off Procedures
2. Place AM64x boot switch selectors (SW2, SW3) into selected boot mode. For more details, see the bootmode section. AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 9: Power-Off Procedure
1. Switch EVM power switch (SW1) to OFF position. 2. Disconnect AC power from AC/DC converter. 3. Remove DC power plug from EVM power jack (J6). SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 10: Peripheral And Major Component Description
PCIe reference clock from the SoC (SERDES0_REFCLK0) will be provided to the PCIe slot connector during root complex mode of operation. AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 11: Reset
AM64x to manually assert reset to the peripheral. Figure 3-5. Overall Reset Architecture of the AM64x EVM SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 12: Power
10mΩ ± 0.5% VCC1V8 SoC_DVDD1V8 10mΩ ± 0.5% VDDA1V8 VDDA_1V8 10mΩ ± 0.5% VCC1V2_DDR VDD_DDR4 10mΩ ± 0.5% AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 13: Power Supply
VDD_1V0 TP56 VPP_DDR_2V5 TP47 2.5 V VDDR_VTT TP48 0.6 V VCC1V8 TP51 1.8 V VPP_1V8 TP52 1.8 V SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 14: Figure 3-6. Power Good Leds
VCC_5V0 LD15 VCC3V3_PREREG VCC_3V3_SYS VDD_2V5 VDD_1V1 LD10 VDDA1V8 VDD_CORE VCC_CORE VDD_2V8 LD25 VCC1V2_DDR Figure 3-6. Power Good LEDs AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 15: Power Sequencing
Power Up and Power Down sequence of all the Power supplies present on the EVM Board. Figure 3-7. Power ON and OFF Sequencing SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 16: Soc Power
General VDDSHV1 PRG0 VDDSHV2 PRG1 VDDSHV3 GPMC VDDA_1V8_MCU VDDA_MCU VDDA_MCU_ADC VDDA_ADC ADC0 VDDA_1V8_SERDES VDDA_1P8_SERDES0 SERDES0 VDDA_1V8_USB0 VDDA_1P8_USB0 USB0 AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 17: Configuration
“OFF” corresponds to logic “LOW”. For a full description of all AM64x SoC supported bootmodes, see the AM64x Sitara™ Processors Data Manual AM64x Processors Silicon Revision 1.0 Texas Instruments Families of Products Technical Reference Manual. The following boot modes are supported by EVM: 1. -
Page 18: Figure 3-9. Am64X Gp Evm Schematic Excerpt, Boot Mode Selection Switches (Sw2, Sw3)
The BOOTMODE pins provide means to select the boot mode before the device is powered up. They are divided into the following categories: Note The following bitpattern is reversed in the table from the switch order AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 19: Table 3-7. Bootmode Bits
Reserved OSPI QSPI Reserved Reserved UART MMC/SD Card eMMC GPMC NAND GPMC NOR PCIe xSPI No-boot / Dev-boot SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 20: Table 3-10. Primary Boot Media Configuration Bootmode[9:7]
Boot Device Rsvd None Mode Rsvd Reserved Rsvd UART Rsvd Reserved Port MMC/SD Rsvd Rsvd BOOTMODE[14:15] - Reserved AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 21: Jtag
Pin No. Signal JTAG_CTI_TMS JTAG_CTI_TCK JTAG_TRSTN DGND JTAG_CTI_TDI JTAG_EMU0 JTAG_TDIS JTAG_EMU1 VCC_3V3_SYS JTAG_EMU_RSTN DGND JTAG_TDO SEL_XDS110_INV JTAG_CTI_RTCK DGND DGND SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 22: Figure 3-11. Jtag Interface
Pin No. Signal Pin No. Signal VCC3V3_R MIPI_TRC_DAT06 MIPI_TMS_R JTAG_MIPI_TCK MIPI_TRC_DAT07 MIPI_TDO_R MIPI_TDI_R MIPI_TRC_DAT08 MIPI_EMU_RSTn MIPI_RTCK MIPI_TRC_DAT09 MIPI_TRST#_R JTAG_MIPI_EMU0 AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 23: Test Automation
The bootmode selection switches should be in the OFF condition and GPIO3 should be set to logic low to enable this mode. SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 24: Figure 3-12. Test Automation Header
The other I2C interface is connected to the current measurement and temperature sensing devices present on the I2C1 port of the SoC. The Test Automation connector is used by Texas Instruments for control of software regression testing and comparative power measurements. The connector is provided to allow customers to develop their own testing and power measurements of customer applications. -
Page 25: Table 3-17. Test Automation Header (J38) Pin-Out
TEST_GPIO4 Input DGND Ground SOC_I2C1_SCL Bidirectional BOOTMODE_I2C_SCL Bidirectional SOC_I2C1_SDA Bidirectional BOOTMODE_I2C_SDA Bidirectional DGND Ground DGND Ground DGND Ground SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 26: Uart Interface
Edit Mode is used to edit the settings of an EEPROM template • Program Mode is used to Program and Erase the device EEPROM(s). Figure 3-13. UART Interface AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 27: Memory Interfaces
(single chip). The placement and routing of the DDR4 device will be point to point with VTT termination. The DDR4 requires 1.2V and thus reduces power demand. Figure 3-14. DDR4 Interface SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 28: Mmc Interface
CAP_VDDSHV_SDLDO pin. CAP_VDDSHV_SDLDO is connected to both the IO voltage of SD signals and VDDSHV_MMC1 power pins of the SoC. Figure 3-15. Micro SD Interface AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 29: Ospi Interface
Remove 0E resistors from the following 1. OSPI_DQ4 to OSPI_DQ7 nets (R432, R441, R442, R443) 2. OSPI_INTn (R158) SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 30: Spi Eeprom Interface
VendorID Build_Week week of the year of production Build_Year year of production BoardID Serial_Nbr incrementing board number AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 31: Ethernet Interface
The objective of the PHY used to connect this port is that the PHY should support both RGMII and MII modes, hence DP83869 (48 pin) PHY is selected. SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 32: Figure 3-19. Ethernet Interface - Icssg Domain
CPSW_RGMII1 used for the first PHY). Hence the same DP83869 (48pin) PHY is used for this port as well. Figure 3-19. Ethernet Interface - ICSSG Domain AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 33: Dp83867 Phy Default Configuration
01111 (0Fh) using the strap resistors. Footprint for both pull up and pull down is provided on all the strapping pins. SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 34: Table 3-19. Default Strap Setting Of Cpsw Ethernet Phy
LEDCR1 register address 0x0018 on the DP83867 device and LEDS_CFG1 register address 0x0018 on the DP83869 device. The default configuration are as follows. AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... - Page 35 LED1 is connected to RJ45 LED (Green) to indicate 1000MHz speed LED2 is connected to RJ45 LED (Yellow) to indicate transmit/receive activity. SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated...
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Page 36: Figure 3-20. Ethernet Interface - Cpsw Ethernet Strap
System Description www.ti.com Figure 3-20. Ethernet Interface - CPSW Ethernet Strap Settings AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 37: Figure 3-21. Ethernet Interface - Icssg1 Ethernet Strap Settings
System Description Figure 3-21. Ethernet Interface - ICSSG1 Ethernet Strap Settings SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 38: Figure 3-22. Ethernet Interface - Icssg2 Ethernet Strap Settings
Figure 3-22. Ethernet Interface - ICSSG2 Ethernet Strap Settings Note Resistors that are highlighted by red color box are DNI components. AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 39: Ethernet Leds
IO Expander, which is controlled by the SoC via the I2C1 port. These eight LED’s can be toggled based on the user application. Figure 3-23. GP Board Ethernet Interface - LEDs SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 40: Display Interface
Table 3-21. Table 3-21. Display Connector (J36) Pin-Out Pin No. Signal VDDB RES# IREF VCOMH AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 41: Usb 2.0 Interface
MCU_PORz pin. The reset signal is connected to 3 pin header and the selection should be made with a jumper. The JTAG signals are unused and test points are provided on the signals. SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 42: Figure 3-25. Pcie Interface
GROUND REFCLK- SERDER_REFCLK0N PETp0 SERDES_TXP0 GROUND PETn0 SERDES_TXN0 PERp0 SERDES_RXP0 PERn0 SERDES_RXN0 PRSNT2#_1 J35.2 GROUND GROUND RSVD1 PETp1 AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 43: High Speed Expansion Interface
VCC_5V0_HSE SOC_SPI1_MISO VCC_5V0_HSE SOC_SPI1_MOSI VCC_5V0_HSE DGND PRG0_MDIO0_MDIO PRG0_PRU1GPO8 PRG0_MDIO0_MDC DGND DGND DGND PRG0_PRU0GPO8 PRG0_PRU0GPO7 PRG0_PRU0GPO2 PRG0_PRU0GPO17 PRG0_PRU0GPO3 PRG0_PRU0GPO18 SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... - Page 44 DGND GPMC0_CSN2 DGND GPMC0_CSN3 DGND DGND GPMC0_AD12 GPMC0_AD13 HSE_GPIO0_32 HSE_GPIO0_33 HSE_GPIO0_34 HSE_PRG0_PRU1_GPO7 HSE_GPIO0_37 HSE_MCAN0_TX/UART4_RXD DGND DGND HSE_GPIO0_39 HSE_GPIO0_41 AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated...
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Page 45: Figure 3-26. High Speed Expansion Connector
DGND DGND PRG0_PRU1GPO6 HSE_GPIO0_38 PRG0_PRU1GPO14 HSE_PRG0_PRU1_GPO10 PRG1_PRU1GPO18 DGND GPMC0_AD0 DGND GPMC0_AD3 MCU_PORZ Figure 3-26. High Speed Expansion Connector SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 46: Figure 3-27. High Speed Expansion Connector Part 1
System Description www.ti.com Figure 3-27. High Speed Expansion Connector Part 1 AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 47: Can Interface
Table 3-25. CAN (J31 and J32) Pin-out CAN0 J31 CAN1 J32 Pin No. Signal Pin No. Signal MCAN0_H MCAN0_H MCAN0_L MCAN0_L SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 48: Interrupt
DGND ADC0_AIN7 DGND ADC0_AIN6 DGND VDDA_ADC ADC0_AIN1 DGND ADC0_AIN0 ADC0_AIN2 DGND ADC0_AIN5 VDDA_ADC DGND ADC0_AIN3 DGND ADC0_AIN4 DGND AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 49: Safety Connector
J5 for AM64x processor slave operation. Pin outs of I2C test header is given in Table 3-28. Table 3-28. I2C Test Header (J5) Pin-out Pin No. Signal DGND SoC_I2C0_SDA SoC_I2C0_SCL SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 50: Table 3-29. I2C Test Header (J4) Pin-Out
4. MCU_I2C0: This is connected to the safety connector. 5. MCU_I2C1: This is connected to the safety connector. AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 51: Figure 3-30. I2C Interfaces And Address Assignment To Its Peripherals
System Description Figure 3-30 depicts the I2C tree. Figure 3-30. I2C Interfaces and Address Assignment to its Peripherals SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 52: Fsi Interface
Table 3-30. FSI (J5) Connector Pin-out Pin No. Signal FSI_TX0_CLK FSI_RX0_CLK DGND DGND FSI_TX0_D0 FSI_RX0_D0 FSI_TX0_D1 FSI_RX0_D1 DGND VCC_3V3_SYS Figure 3-31. FSI Interface AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 53: Known Issues And Modifications
2. EVM power is enabled and the AM64x is brought up in no-boot mode. 3. In CCS, an initial CCS target connection to the M3 DMSC core is then attempted. SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 AM64x GP EVM User's Guide Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 54: Figure 4-2. Xds110 Ccs Connection Error Dialog
PC. A similar tool is available under the Linux OS install of CCS. Figure 4-3. : XDS110 debug reset utility command-line function AM64x GP EVM User's Guide SPRUIX0B – FEBRUARY 2021 – REVISED MARCH 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated... -
Page 55: Issue 2 - Mdio Ethernet Phy Communications
• AM64x Sitara™ Processors Data Manual • AM64x Processors Silicon Revision 1.0 Texas Instruments Families of Products Technical Reference Manual 6 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2021) to Revision B (March 2021) Page •... - Page 56 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2021, Texas Instruments Incorporated...
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