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This technical User's Guide describes the hardware architecture of the AM65x GP EVM. The AM65x
processor is part of the K3 Multicore SoC architecture platform Arm.
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SPRUIM7 - October 2018
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Copyright © 2018, Texas Instruments Incorporated
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User's Guide
SPRUIM7 - October 2018
AM654x GP EVM
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AM654x GP EVM
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Table of Contents
Related Manuals for Texas Instruments AM654 Series
Summary of Contents for Texas Instruments AM654 Series
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Page 1: Table Of Contents
Strapping Diagram for MCU and PRG2-RGMII1 Ethernets ................ Strapping Diagram for PRG2-RGMII2 Ethernet ..................CP Board Ethernet Interface – LEDs ................... J4 Header for USB2.0 Host Interface SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 2 I2C Test Header (J33) Pin-out ....................SPI1 Header (J20) Pin-out ............ Resistors for Selecting CS Signals for Test Automation Header ......................Timer Pin Selection ....................Timer Header(J19) Pin-out AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 3 Selection of Reference Clock for PCIe Endpoint Operation ................... Board ID Memory Header Information Trademarks Code Composer Studio is a trademark of Texas Instruments. Arm, Cortex are registered trademarks of Arm Limited. SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback...
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Page 4: Introduction
DC Input: 11 V to 28 V • Status output: LEDs to indicate power status • INA devices for current monitoring • Over- and under-voltage protection circuit • RoHS-compliant design AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 5: Am65X Gp Evm Overview
The AM65x GP EVM consists of a common processor board, an LCD adapter, and a one-lane PCIe/USB3 personality card. Detailed descriptions of these cards are explained in the following sections. SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 6: Common Processor Board
Common Processor Board www.ti.com Common Processor Board Figure 3. Top View of the Common Processor Board AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 7: Key Features
Full size SD card, up to 64-GB density with UHS-1 support • 128-Mbit SPI EEPROM • 512-Mbit OSPI EEPROM • 256-Kbit I2C EEPROM for Boot SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 8 (ABM3-25.000MHZ-D2Y-T, ABM3-12.000MHZ-D2Y-T) from Abracon LLC that contains two Substance of Very High Concern (SVHC) above 0.1%. These uses from Texas Instruments do not exceed 1 ton per year. The SVHC’s are Diboron trioxide CAS#1303-86-2 and Lead Oxide CAS# 1317-36-8.
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Page 9: Functional Block Diagram
Functional Block Diagram The functional block diagram of the common processor board is shown in Figure Figure 5. Common Processor Board Functional Block Diagram SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 10: Overview Of Common Processor Board
GP EVM EVM. A 32.768-kHz quartz crystal is used to provide the clock for the RTC device. The RTC device generates 32.768-kHz square wave output, which is connected to WKUP_LFOSC input of the SoC. AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 11: Am65X Gp Evm Clock Tree
WKUP_OSC 0, resistor R448 must be mounted and resistors R450 and R457 removed. LFOSC: The 32.768-KHz square wave is provided by the MFP output of the RTC component. SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 12 (default), and short pin 1 and 2 to bypass the internal POR. Most peripheral resets are “ANDED” with the POR output from the SoC along with a GPIO control, as shown in Figure AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
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Page 13: Overall Reset Architecture Of The Am65X Gp Evm
Common Processor Board www.ti.com Figure 7. Overall Reset Architecture of the AM65x GP EVM SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 14: Connectors Used For Power Input
The safe operation input voltage range is 11 V to 28 V. A fault indication and power good LEDs are provided to indicate the power status. AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 15 +/- 5% VCC_12V0 TP66 12.0 V +/- 5% VCC3V3_IO TP20 3.3 V +/- 5% VDDR_VTT 1.65 V +/- 5% VCC_2V5 TP82 2.5 V +/- 5% SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 16 +/- 5% VDD_1V0 TP27 1.0 V +/- 5% VCC1V8 TP19 1.8 V +/- 5% Table 5. Power LEDs Sl # Power Supply VCC3V3_PREREG VCC_5V0 VCC_12V0 AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
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Page 17: Power On Sequencing
VDDSHV6 MMC0 1.8 V VDDSHV_MMC1 VDDSHV7 MMC1 1.8 V VDDSHV_WKUP_GENERAL VDDSHV0_WKUP MCU_GENERAL 3.3 V VDDSHV_WKUP_FLASH VDDSHV1_WKUP MCU_FLASH 1.8 V VDDSHV_WKUP_CPSW2G VDDSHV2_WKUP MCU_CPSW2G 1.8 V SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 18: Bootmode Bits
The BOOTMODE pins provide the means to select the boot mode before the device is powered up. They are divided into the following categories. Figure 10. BOOTMODE Bits AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 19 When the min pin value is 1, all configuration fields are based on pre-defined default values. In this case, no boot mode pins beyond the min pin need to be driven because their values are ignored. SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 20 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved Fail Safe mode Ref Clock Select AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
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Page 21: Boot Switches Provided On The Processor Card
No fail-safe boot supported I2C port 0 SPI Port 0 Hyperflash Port 0 MCU_BOOTMODE[10:5]- Reserved Figure 11. BOOT Switches Provided on the Processor Card SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 22 Table 17. TI 60-pin Connector (J32) Pin-out Pin No. Signal Pin No. Signal VCC3V3 MIPI_TRC_DAT06 MIPI_TMS MIPI_TCK MIPI_TRC_DAT07 MIPI_TDO MIPI_TDI MIPI_TRC_DAT08 MIPI_EMU_RSTn MIPI_RTCK MIPI_TRC_DAT09 MIPI_TRSTN JTAG_MIPI_EMU0_1V8 MIPI_TRC_DAT10 JTAG_MIPI_EMU1_1V8 AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 23 GPIO3 should be set to logic low to enable this mode. The other I2C interface is connected to the current measurement and temperature sensing devices present on the I2C2 port of the SoC. SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 24 Common Processor Board www.ti.com The test automation connector is used by Texas Instruments to control the software regression testing and comparative power measurements. The connector is provided to allow customers to develop their own testing and power measurements of customer applications. Power measurements are not a substitute for the AM65x Power Estimation Tool and should not be used for the design of power supply solutions.
- Page 25 The test headers (J11 and J30) pin out is given in Table Table 21. UART Connectors (J11 and J30) Pin Out Pin No. MCU_UART0 J30 WKUP_UART0 J11 SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
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Page 26: Ddr4 Interface
ECC. The DDR4 interface can operate up to 1600 MT/s speed. The DDR4 devices are connected using flyby routing for the address/command lines, and point-to-point connection for the data bus. Figure 12. DDR4 Interface AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 27: Sdhc Interface
1.8 V and 3.3 V. The I/O voltage is controlled using the internal SDIO_LDO, which provides the I/O voltage for the MMC1 port. Figure 13. SDHC Interface SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 28: Emmc Interface
MMC0 port of the AM65x processor. The flash is connected to 8bits of the MMC0 interface supporting HS400 double data rates up to 200 MHz. Figure 14. eMMC Interface AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 29: Ospi Interface
AM65x processor. In addition, SPI0 is also connected to the application connector and test automation header. SPI_CS0 and SPI_CS1 chip select signals are used for the serial flash and application connector, respectively. SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 30 A 256-Kbit EEPROM is interfaced to WKUP_I2C for booting. Earlier versions of the board had this memory address set to 0x54. Later versions have the address set to 0x52. AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
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Page 31: Ethernet Interface - Mcu Domain
MCU domain and two RGMII ports (connected to stacked RJ45 connector J14A and J14B) from ICSSG (PRG2) domain of the AM65x processor are used. Figure 16. Ethernet Interface – MCU Domain SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 32: Ethernet Interface - Icssg Domain
Mode 3 – 0.405 V to 0.5112 V Mode 4 – 1.2492 V to 1.5984 V Default configurations of all phys are mentioned in Table AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 33 Open Open RGMII Clock Skew RX[0]=0 RGMII Clock Skew RX = 2 GPIO_1 Open Open RGMII Clock Skew RX[2]=0 and RGMII Clock Skew RX[1]=0 SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
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Page 34: Strapping Diagram For Mcu And Prg2-Rgmii1 Ethernets
Common Processor Board www.ti.com Figure 18. Strapping Diagram for MCU and PRG2-RGMII1 Ethernets AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 35: Strapping Diagram For Prg2-Rgmii2 Ethernet
Common Processor Board www.ti.com Figure 19. Strapping Diagram for PRG2-RGMII2 Ethernet SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 36 1000-Mb link. The green LED indicates 10/100-Mb speed, and the orange LED indicates 1000-Mb speed. LED2 is connected to RJ45 LED (Yellow) to indicate transmit/receive activity. AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
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Page 37: Cp Board Ethernet Interface - Leds
20720-040E-02. It is a 0.5-mm pitch Shielded FFC / FPC connector. The PWM output signal from the AM65x processor is terminated to the I-PEX connector, which is used to drive the back-light circuit in the adapter card. SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 38: Usb 2.0 Interface
DRVVBUS0 for host / slave detect and power enable. The USB1 port is terminated to a uAB connector (J3) and supports both host and slave mode. AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... -
Page 39: J4 Header For Usb2.0 Host Interface
KC2520B24.0000C1GE00 is provided to supply 24-MHz REFCLK to the CSI-2 module. Mount U114 for 1.8-V REFCLK, and mount U112 for 3.3-V REFCLK. SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 40 CP Card Signals-CSI Direction CSI_MCU_SCL Output CSI_MCU_SDA Bidirectional CSI0_RXP0 Input CSI0_RXN0 Input CSI0_RXP1 Input CSI_REF_CLK Output CSI0_RXN1 Input DGND Power CSI0_RXP2 Input CSI_RESETN Output AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 41 Power DGND DGND DGND CSI0_RXP0 Input CSI0_RXN0 Input DGND Power CSI0_RXP1 Input CSI0_RXN1 Input DGND Power CSI0_RXP2 Input CSI0_RXN2 Input DGND Power CSI0_RXP3 Input SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 42 R576 Mount R580 Mount R578 Mount R574 Mount R572 Mount R587 Mount R569 Mount R590 Mount R575 Mount R579 Mount R577 Mount R573 Mount AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 43 DGND Power PRG1_RGMII1_ETH1_CLK ETH0_CLK Output PRG0_RGMII1_ETH1_CLK ETH1_CLK Output DGND DGND Power DGND DGND Power PRG0_PRU0GPO15 ETH0_RGMII_TD3 Output APP_PRG0_PRU1GPO5 PRG0_PRU0GPO13 ETH0_RGMII_TD1 Output APP_PRG0_PRU0GPO17 ETH_LED1 Output SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 44 Output PRG0_PRU1GPO10 ETH2/3_INTN Input PRG0_PRU1GPO12 ETH1_RGMII_TD0 Output PRG0_PRU1GPO18 PRG0_IEP1_LATCH_IN0 Input DGND DGND Power PRG0_MDIODATA ETH0/1_MDIO Bidirectional PRG0_PRU1GPO6 ETH1_RGMII_RXC input PRG1_PRU1GPO5 DGND DGND Power PRG1_PRU1GPO8 AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 45 DGND DGND Power PRG1_PRU0GPO11 ETH2_RGMII_TX_CTL Output PRG1_MDIODATA ETH2/3_MDIO Bidirectional PRG1_PRU0GPO14 ETH2_RGMII_TD2 Output DGND DGND Power PRG1_PRU0GPO15 ETH2_RGMII_TD3 Output PRG1_RGMII2_ETH2_CLK ETH3_CLK Output DGND DGND Power SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 46 DGND Power SOC_SPI0_CLK IDK_SPI_CLK_3V3 Output SOC_I2C0_SCL IDK_I2C_SCL_C Output DGND DGND Power SOC_I2C0_SDA IDK_I2C_SDA_C Bidirectional SOC_SPI0_CS1 IDK_SPI_CSN_3V3 Output DGND DGND Power SOC_SPI0_D0 UART1_CTS PRG1_IEP1_LATCH_IN0 Output AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 47 SERDES daughter cards to interface with the processor card. The PCIe lanes can be configured a single 2-lane port or two 1-lane ports independently. The pin-out of SERDES connector is shown in Table SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 48 USB0_DP Bidirectional DGND Power USB0_PCIE0_SGMII0_RXP0 Input USB0_PCIE0_SGMII0_RXN0 Input DGND Power USB0_PCIE0_SGMII0_TXP0 Output USB0_PCIE0_SGMII0_TXN0 Output DGND Power SERDES_BRD_DET Input GPIO_SGMII_PHY_INT Input USB0_VBUS Power DGND Power AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 49 The board supports an option to mount a 60-pin connector (QSH-030-01-L-D-A-K) or a 120-pin connector (QSH-060-01-L-D-A-K). These connector footprints are overlapped such that only one of them can be mounted. By default, the 60-pin connector is mounted. SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 50 VOUT_D8_BOOTMODE8 Bidirectional SOC_MCU_SDA Bidirectional DGND Power DGND Power VOUT_D7_BOOTMODE7 Bidirectional GP1_TOUCH_EVT Output VOUT_D6_BOOTMODE6 Bidirectional CON_LCD_PWR_DN Output VOUT_D5_BOOTMODE5 Power SOC_SPI1_CS1 Output VOUT_D4_BOOTMODE4 Bidirectional SOC_SPI1_MOSI Output AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 51 SOC_SPI1_CLK Output VOUT_D1_BOOTMODE1 Bidirectional USB1_HDMI_GPMC_DRVBUS Output VOUT_D0_BOOTMODE0 Bidirectional USB1_HDMI_GPMC_DM Bidirectional USB1_HDMI_GPMC_DP Bidirectional VCC_5V0 Power VCC3V3_IO Power VCC_5V0 Power VCC3V3_IO Power VCC_5V0 Power VCC3V3_IO Power SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 52 Pin outs of the I2C test header is given in Table Table 33. I2C Test Header (J33) Pin-out Pin no. Signal DGND I2C0_SDA I2C0_SCL AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 53 One test header for I2C0 is provided for any external validation. Figure 24 Figure 25 depicts the I2C tree. Figure 24. I2C Interfaces and Address Assignment to its Peripherals (1 of 2) SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 54 SPI_CS1 is connected to the GPMC/DSS connector. The chip selects SPI1_CS0 and SPI_CS1 are also connected to the test header, through resistors (R316 and R317) as shown in Table 35. By AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 55 3.3-V I/O level. The MCU_SPI interface signals are powered by the VDDSHV_WKUP_GENERAL power supply of SoC and are at the 3.3-V I/O level. SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 56 Common Processor Board www.ti.com Figure 26. SPI Tree AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
- Page 57 These interrupts are implemented with a Schmitt-trigger buffer and RC delays to avoid any de-bounce effects triggering the interrupts. The push-button SW5 is mapped to WKUP_GPIO0_13, and SW6 is mapped to WKUP_GPIO0_27. SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
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Page 58: X1 Lane Pcie/Usb3 Personality Card
A 10-pin power connector for DC input: 3.3 V, 2.5 V, 1 V, 1.8 V, and 5 V • Powered by MAXWELL common processor board AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 59 Lane PCIe/USB3 Personality Card www.ti.com Figure 30. x1 Lane PCIe/USB3 Personality Card Block Diagram SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
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Page 60: Overview Of Pciex1/Usb3 Daughter Card
For PCIe RC operation, the reference clock can be sourced directly from the SOC to the PCIe EP or from the clock generator to the SoC and PCIe EP. Selection can be made through jumpers, as shown in Table AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 61 VendorID Build_Week week of the year of production Build_Year year of production BoardID Serial_Nbr incrementing board number END_LIST TYPE End Marker SPRUIM7 – October 2018 AM654x GP EVM Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated...
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Page 62: Known Issues
SOLUTION: Customers should select a crystal with a load capacitance that is within the range specified in the data manual. AM654x GP EVM SPRUIM7 – October 2018 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated... - Page 63 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2018, Texas Instruments Incorporated...
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