Analog Devices Blackfin FPGA EZ-Extender Manual page 60

INDEX
FPGA
documentation, 1-2,
input jumpers (JP5),
software/firmware, 1-2
Xilinx Spartan package, -x,
FPGA pins
AB10 (LED3), 2-17
AB11 (JP5.8), 2-15
AB8 (LED7), 2-17
AB9 (LED5), 2-17
C11 (PB1/SW3), 2-15
H5 (PB2/SW3), 2-16
M2-0 (JP4), 2-14
U10 (JP5.6), 2-15
U11 (LED1), 2-17
V10 (LED8), 2-17
W11 (LED2), 2-17
W9 (LED6), 2-17
Y10 (LED4), 2-17
Y3-2 (JP5.2-5.4), 2-15
FPGA programming
block diagram, 2-3
via ADSP-BF533/37/6 processors,
via JTAG header, 2-4
via serial ROM, 2-5
G
GCLK1 (global clock 1) pin,
GCLK6 (global clock 6) pin,
general-purpose input push buttons, 2-15,
H
high-speed connector (P4),
I
IDC connectors, -x, 2-19,
installation, of this EZ-Extender,
I-2
2-6
2-14
1-3
2-6
1-4
1-4
2-16
2-20
2-20
1-1
J
JTAG
cable, 1-4, 2-7
header (P6), 1-5, 2-4, 2-7,
jumpers
map of locations, 2-11
JP1 (boot jumper), 2-5,
JP2 (config done), 2-12
JP3 (config program),
JP4.1-4.6 (boot mode select), 2-5, 2-6,
JP5.2-5.6 (FPGA input),
L
LEDs
map of locations, 2-15
LED10 (FPGA done pin), 2-4, 2-5,
LED1-8 (status), 2-17
LED9 (power), 2-17
M
M2-0 (JP4) pins, 2-5
master serial boot mode,
MCS-86 Hexadecimal Object (.mcs) file
format, 2-6
N
notation conventions, -xvi
O
oscillator, -x, 1-4
P
P12 (power in) header,
P13 (3.3V header), 2-9
P42 (2.5V header), 2-10
P43 (1.2V header), 2-10
PB1 push button (SW3),
Blackfin FPGA EZ-Extender Manual
2-14
2-12
2-13
2-14
2-14
2-17
2-6
2-9
2-15