Analog Devices Blackfin FPGA EZ-Extender Manual page 48

A
FLASH JTAG HEADER
3.3V
1
P6
1
2
3
FLASH_TCK
4
FLASH_TDO
5
FLASH_TDI
6
FLASH_TMS
IDC6X1
2
U2
2
FLASH_DOUT 1A
5
2A
11
3A
4
1Y
14
4A
7
2Y
9
3Y
3
DT1PRI 1B
12
4Y
6
2B
10
3B
13
4B
15
EN
1
FLASH_DONE ~A/B
74LVC157
TSSOP16
3
3.3V
3.3V
25MHZ SYSTEM CLOCK
R29
10K
0603
R2
U6 4 33.0
VDD 0603
1 3
OE OUT
GND
25MHZ 2
OSC003
1.2V
4 C17 C18 C19 C20 C21 C22
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
0603 0603 0603 0603 0603 0603
FPGA
A
B
3.3V
FPGA BOOT FLASH
R1
10K
0603
U4
3
CONFIG_CLK_TSCLK1 CLK
1
FLASH_DOUT D0
8
CONFIG_INIT_B_TFS1 OE/~RESET
JP1 10
CE
1 2 FLASH_DONE
CONFIG_DONE
7
CF
IDC2X1
13
CEO
5
FLASH_TMS TMS
6
FLASH_TCK TCK
4
FLASH_TDI TDI
17
FLASH_TDO TDO
XCF04S
TSSOP20
BOOTMODE JUMPER
CONFIG_DIN_DT1PRI
M0
M1
M2
3.3V
EXTRA CLOCK SOCKET
R25
10K
0603
DNP U7
1
B4_L32N_GCKL1_AA12 OE/NC
DIP
DIP8SOC
C23 C24 C25 C15 C16 C26
0.01UF 0.01UF 0.01UF 10UF 10UF 0.01UF
0603 0603 0603 0805 0805 0603
B
FPGA JTAG HEADER
(2Mbit)
3.3V
P15
1
2
3
18
VCCINT
4
19
VCCO
5
20
VCCJ
6
IDC6X1
2
NC1
9
NC2
12
NC3
14
NC4
15
NC5
16
NC6
11
GND
JP4
1 2
3 4
5 6
IDC3X2
SW1
SWT013
MOMENTARY
R26
33.0
5 0603
OUT IO_L32_0_GCLK6_A11
2.5V
OSC
C27 C31 C30 C29 C28 C14
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 10UF
0603 0603 0603 0603 0603 0805
FPGA
C
3.3V
FPGA_TCK
FPGA_TDO
FPGA_TDI
FPGA_TMS
3.3V
R22 R28 R6 R21
10K 10K 10K 10K
0603 0603 0603 0603
R44
100
0402
FPGA_TCK
R8
100
0402
FPGA_TDI
FPGA_TDO
R7
100
0402
FPGA_TMS
R4
33.0
0603
CONFIG_CLK_TSCLK1
CONFIG_PROG_B
R5
100
0402
CONFIG_DONE
LED10
YELLOW
LED001
R24
330
3.3V 0603
C32 C11 C12 C13
0.01UF 0.01UF 0.01UF 0.01UF
0603 0603 0603 0603
SKT FLASH MUX
ANALOG
DEVICES
BLACKFIN FPGA EZ-EXTENDER
Title
Size Board No.
C
Date 5-4-2006_11:44
C
D
1.2V 2.5V
U1
A6 J10
VCCAUX_A6 GND_J10
A17 J11
VCCAUX_A17 GND_J11
F1 J12
VCCAUX_F1 GND_J12
F22 J13
VCCAUX_F22 GND_J13
U1 J14
VCCAUX_U1 GND_J14
U22 J20
VCCAUX_U22 GND_J20
AB6 K9
VCCAUX_AB6 GND_K9
AB17 K10
VCCAUX_AB17 GND_K10
K11
GND_K11
G7 K12
VCCINT_G7 GND_K12
G8 K13
VCCINT_G8 GND_K13
G15 K14
VCCINT_G15 GND_K14
G16 L9
VCCINT_G16 GND_L9
H7 L10
VCCINT_H7 GND_L10
H16 L11
VCCINT_H16 GND_L11
R7 L12
VCCINT_R7 GND_L12
R16 L13
VCCINT_R16 GND_L13
T7 L14
VCCINT_T7 GND_L14
T8 M9
VCCINT_T8 GND_M9
T15 M10
VCCINT_T15 GND_M10
T16 M11
VCCINT_T16 GND_M11
M12
GND_M12
A21 M13
TCK GND_M13
B1 M14
TDI GND_M14
B22 N9
TDO GND_N9
A20 N10
TMS GND_N10
N11
GND_N11
AB2 N12
M0 M0 GND_N12
AA1 N13
M1 M1 GND_N13
AB3 N14
M2 M2 GND_N14
P3
GND_P3
AA22 P9
CCLK GND_P9
A2 P10
PROG_B GND_P10
AB21 P11
DONE GND_P11
B3 P12
HSWAP_EN GND_P12
P13
GND_P13
A1 P14
GND_A1 GND_P14
R3
0 A22 P20
GND_A22 GND_P20
0603
B2 Y9
GND_B2 GND_Y9
B21 Y14
GND_B21 GND_Y14
C9 AA2
GND_C9 GND_AA2
C14 AA21
GND_C14 GND_AA21
J3 AB1
GND_J3 GND_AB1
J9 AB22
GND_J9 GND_AB22
XC3S1000
FG456
20 Cotton Road
Nashua, NH 03063
PH: 1-800-ANALOGD
FPGA CONFIG
Rev
A0199-2005
1.0B
Sheet 2 of 12
D
1
2
3
4