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Advantech PCL-833 User Manual

3-axis quadrature encoder and counter card
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PCL 833
3 axis quadrature encoder
and counter card

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  • Page 1 PCL 833 3 axis quadrature encoder and counter card...
  • Page 2 A c k n o w l e d g m e n t s PC-LabCard is a trademark of Advantech Co., Ltd. IBM and PC are trademarks of International Business Machines Corporation. MS- DOS, Microsoft C and Quick Basic are trademarks of Microsoft Corporation.

  • Page 3: Table Of Contents

    C o n t e n t s Chapter 1 General information ........1 Introduction ................2 Encoder interface ................2 Counters ..................2 Digital input and interrupts ............2 Features .................. 3 Applications ................3 Specifications ................. 4 Encoder input .................4 Digital input ...................4 Programmable interrupt controller ..........4 General ...................4 Block diagram ...............
  • Page 4 Cascade mode ..............20 Timer function ..............21 Interrupt function ............... 22 Chapter 4 Programming ..........2 3 Driver programs ..............24 Basic program structure ............. 24 Driver functions ..............25 Write functions ................25 Read functions ................28 Compiling and linking with C compilers ......28 Borland C ..................28 Microsoft C ..................29 Chapter 5...

  • Page 5: Chapter 1 General Information

    General information Chapter 1 General information 1...

  • Page 6: Introduction

    I n t r o d u c t i o n The PCL-833 is a 3-axis quadrature encoder and counter add-on card for the IBM PC/AT and compatibles (ISA bus). This card lets your PC perform position monitoring for motion control systems. It provides three 24-bit up/down counters as quadrature encoders and a 16-MHz oscillator timebase with wide-range multiplier.

  • Page 7: Features

    F e a t u r e s • Three 24-bit up/down counters (cascade for up to 48 bits) • 1.0 MHz max quadrature input rate • 2.4 MHz max. input pulse rate • Single ended or differential inputs • Pulse/direction and up/down counter •...

  • Page 8: Specifications

    S p e c i f i c a t i o n s Encoder input • No. of Axes: Three independent axes • Max. quadrature input freq.: 1.0 MHz • Max. input pulse freq.: 2.4 MHz • Counts per encoder cycle: 1, 2 or 4 (s/w selectable) •...

  • Page 9: Block Diagram

    Block diagram C H . 1 P H A S E A 2 4 - B I T C O U N T E R D I G I T A L U P / D O W N M O D E C H .
  • Page 10 PCL 833 User's Manual...

  • Page 11: Chapter 2 Installation

    I n s t a l l a t i o n Chapter 2 Installation...

  • Page 12: Initial Inspection

    In addition to this manual the shipping container should contain the PCL-833 card and a utility diskette. We carefully inspected the PCL- 833 mechanically and electrically before we shipped it. It should be free of marks and scratches and in perfect electrical order on receipt.

  • Page 13: Interrupt Level (Jp1)

    Choose a base address that is not in use by any other I/O device. A conflict with another device may cause one or both devices to fail. The factory address setting (hex 200) is usually free as it is reserved for PC prototype boards.
  • Page 14 To use the interrupt you must install an interrupt service routine and program the PCL-833's on-board the 8259 interrupt controller. Nine different conditions can enable the PCL-833's interrupt, but only one at a time. Interrupt source Condition CH1 overflow CH2 overflow...

  • Page 15: Connector Pin Assignments

    Connector assignments You make all connections to the PCL-833 through a single DB-25 connector, shown below: E G N D CH1A- C H 1 A + CH1B- C H 1 B + CH1Z- C H 1 Z + CH2A- C H 2 A +...

  • Page 16: Connector Wiring

    Function CH2B Channel 2 B differential negative input CH2B+ Channel 2 B differential positive input CH2Z Channel 2 Z differential negative input CH2Z+ Channel 2 Z differential positive input CH3A Channel 3 A differential negative input CH3A+ Channel 3 A differential positive input CH3B Channel 3 B differential negative...

  • Page 17: Hardware Installation

    5. Remove the screw that secures the expansion slot cover to the chassis. Save the screw to secure the PCL-833. 6. Carefully grasp the upper edge of the PCL-833 card. Align the hole in the retaining bracket with the hole on top of the expansion slot, and align the gold striped edge connector with the expansion slot socket.

  • Page 18: Software Installation

    Software installation The utility diskette included with the PCL-833 holds a test utility program, example programs and driver programs. We supply the driver as C source code for Borland and Microsoft compilers. To use the driver you compile it along with your program.

  • Page 19: Chapter 3 Operation 15

    O p e r a t i o n Chapter 3 Operation 15...

  • Page 20: Quadrature Encoder Introduction

    Quadrature encoder introduction In typical closed-loop control systems, also know as servo systems, the encoder interface senses motor position and sends a position signal to the controller. The diagram below shows a typical servo system. The encoder generates pulses which indicate the shaft position. The encoder output includes two signals, commonly called channel A and channel B, which generate N pulses per revolution.

  • Page 21: Counter Modes

    Quadrature input consists of two square wave inputs (A and B) which are 90 out of phase. The PCL-833 counts the square wave transitions and determines the direction by comparing whether channel A is leading channel B or vice versa.

  • Page 22: Digital Noise Filter

    A. Disabled mode PCL-833 will not accept input, but you can still access all its registers. You select the mode by programming the card's registers: BASE+0 for CH1, BASE+1 for CH2 and BASE+2 for CH3. See Chapter 5 for more information.

  • Page 23: Latch Mode

    When you read a counter, you are actually reading a value latched into a buffer. The PCL-833 provides five different latching modes, only one of which is active at any given time. Make sure that you know which latching mode is current whenever you read the counter.

  • Page 24: Counter Reset Value

    48 bits of storage. When the first counter over- flows, the card increments the second counter. The PCL-833 lets you cascade channel 1 into channel 2 to form a single 48-bit counter. (Channel 3 will not cascade.)

  • Page 25: Timer Function

    24-bits and channel 2 the low 24-bits. Timer function The PCL-833's on-board timer lets you monitor counter readings with extreme accuracy. The programmable timer generate pulses at regular intervals. The card can latch the readings in its counters and generate an interrupt to the PC.

  • Page 26: Interrupt Function

    Interrupt function The PCL-833 can generate an interrupt to the PC for any of the following conditions: 1. Counter 1 overflow 2. Counter 2 overflow 3. Counter 3 overflow 4. Counter 1 index in 5. Counter 2 index in 6. Counter 3 index in 7.

  • Page 27: Chapter 4 Programming

    P r o g r a m m i n g Chapter 4 Programming...

  • Page 28: Driver Programs

    Driver programs The PCL-833 software driver has predefined routines to set up and control the card. You specify an array of values for the card's registers. The driver modifies the registers in the proper order and sends back the data in a second array.

  • Page 29: Driver Functions

    void main() /* Base address setting. This must match the setting * of switch SW1. */ Base= 0x0200; If you call a read function, the driver will put the data in the array InReg[]. If you read the card's registers directly to get the counter value, instead of using the driver, you must read the highest byte first to ensure whole counter has been latched.
  • Page 30 Function 3: Define reset value argument 1: Ch1_DefineResetValue Ch2_DefineResetValue Ch3_DefineResetValue argument 2: start middle Function 4: Set Latch Source argument 1: Ch1_SetLatchSource Ch2_SetLatchSource Ch3_SetLatchSource argument 2: SwReadLatch IndexInLatch DI0Latch DI1Latch TimerLatch Function 5: Reset/no reset after counter is latched argument 1: Ch1_IfResetOnLatch Ch2_IfResetOnLatch Ch3_IfResetOnLatch argument 2: ResetNo...
  • Page 31 Function 7: Reset/do not reset counter argument 1: CounterReset argument 2: NoneReset Reset_Ch1 Reset_Ch2 Reset_Ch3 Function 8: Choose system clock argument 1: ChooseSysClock argument 2: Sys8MHZ Sys4MHZ Sys2MHZ Function 9: Set cascade mode argument 1: SetCascadeMode argument 2: c24bits c48bits Function 10: Set 16C54 time base argument 1 Set16C54TimeBase...

  • Page 32: Read Functions

    Read functions Function 13: Read counter argument 1: Ch_Read argument 2: ch1 Function 14: Read Overflow argument 1: Overflow_Read argument 2: NA Function 15: Read status argument 1: Status_Read argument 2: NA Compiling and linking with C compilers Borland C Integrated Development Environment (IDE) Create a project file for your program (Project | Create project), e.

  • Page 33: Microsoft C

    Microsoft C The demo programs on the floppy disk are written in Turbo C (Borland C). You will need to modify them slightly to work with Microsoft C. The following example shows how to compile and link the demo programs with Microsoft C: CL /c 833demo1.c CL /c 833mc.c LINK 833demo1.obj + 833mc.obj...
  • Page 34 PCL 833 User's Manual...

  • Page 35: Chapter 5 Register Structure And Format

    Register structure format Chapter 5 Register structure and format...

  • Page 36: Register Format (Read)

    The PCL-833 uses 16 consecutive addresses in the PC I/O address space. DIP switch SW1 sets the card's base, or beginning address. Specific I/O ports are referred to by their offset from the base address, BASE. For example, the address for the seventh register is BASE+6.
  • Page 37 BASE+0, 4, 8 CH1, CH2, CH3 low byte data Value BASE+1, 5, 9 CH1, CH2, CH3 mid byte data D 1 5 D 1 4 D 1 3 D 1 2 D 1 0 Value BASE+2, 6, 10 CH1, CH2, CH3 high byte data Value C 2 3 C 2 2...

  • Page 38: Register Format (Write)

    BASE+14 S t a t u s Value D I 1 D I 0 CH3 ZIN CH2 ZIN CH1 ZIN D2 ~ D0 CH3 ~ CH1 Index status. Digital Input Channel 0 status. Digital Input Channel 1 status. BASE+15 8259 INTA register See Appendix A Register format (write) The following table gives the assignment of each of the card's write...
  • Page 39 BASE+0 CH1 mode setting Value BASE+1 CH2 mode setting Value BASE+2 CH3 mode setting Value M2 ~ M1 Input mode control 0 0 0 Disable 0 0 1 Quadrature input X1 0 1 0 Quadrature input X2 0 1 1 Quadrature input X4 1 0 0 2 pulse input...
  • Page 40 BASE+3 CH1 counter latch source/counter latch on reset Value BASE+4 CH2 counter latch source/counter latch on reset Value BASE+5 CH3 counter latch source/counter latch on reset Value S2, S1, S0 The source of the signal to latch the counter data 0 0 0 S/W read latch data 0 0 1...
  • Page 41 BASE+7 Counter reset Value C H 3 C H 2 CH3 ~ CH1 Reset counter Reset corresponding counter Counter not reset BASE+8 System clock source / cascade mode control Value C A S 1 C A S 0 S Y S 1 S Y S 0 SYS1, SYS0 System clock source 8 MHz system clock 4 MHz system clock...
  • Page 42 BASE+9 16C54 time base and interrupt control Value D I / T I M E R T BASE2 T BASE1 T BASE0 T-BASE 2, 1, 0 16C54 time base control 0 0 0 0.1 msecond time base 0 0 1 1 msecond time base 0 1 0 10 msecond time base...

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