Hitachi FL.NET User Manual page 239

8 APPENDIXES
(4) Data arrangement on circuit
The sequence of data transmitted over a circuit is shown below.
Data transmission begins with address (0) in the relative address 00 column shown below.
Data is transmitted, byte by byte, in the order indicated by the horizontal arrow mark. Upon
completion of the transmission of the data in the relative address 00 column, the data in the
relative address 10 column begins to be transmitted. Transmission continues in the same
manner in the order of relative address.
Relative address
(0)
00 30
10 01
20 "R" "E" "V"
30 0A
40 "A" "T" "E" "G" "O" "R" "Y"
50 "N" "D" "O" "R"
60 "l"
70 "I"
80 "C"
90 "A" "R" "A"
A0 09
B0 "U" "2" "N" "A" "M" "E"
C0 "C" "N"
D0 "M" "S"
E0 "N" "A" "M" "E"
F0 16
100 "W" "D" "6"
110 "-"
120 13
130 "L" "E"
(1) (2) (3) (4) (5)
82 01 33 30 7D
13 02 "I" "D" 13
02 01 00
02 02 07 CE 02
13 1D "M" "S"
"e" "c" "t" "r" "i"
"o" "n" 13 07 "D" "V" "M" "O" "D" "E" "L"
"-" "M" 30 81 B1
30 15 13
"P" "M" "S" "P" "3"
30 15 13 08
"P" "2" "5" "-"
13 09
13 09 "I" "O" "1"
"4" "-" "4" "N"
"0" "N" 30 16 13
09 "N" "A" "M" "E"
"0" "1" "-" "5" "N"
Data (in hexadecimal notation)
(6) (7) (8) (9) (A)
13 06 "C" "O" "M" "V" "E" "R"
07 "S" "Y" "S" "P" "A" "R" "A"
13 07 "R" "E" "V" "D" "A" "T" "E"
01 09 02 01 1E
13 03 "P" "L" "C"
"T" "C" "-"
"c" " " "C" "o" "r"
13 02 "I" "D" 13
08 "C" "P" "U" "1" "N" "A" "M" "E"
"5" "-" "5" "N" 30
13 09 "P" "M" "S"
"P" "U" "3" "N" "A" "M" "E"
"2" "N" 30 15 13
"P" "M" "B" "P" "2"
"0" "5" "N" "A" "M" "E"
30 16 13 09
09 "I" "O" "1" "0"
13 09 "P" "M" "L" "D" "0"
8-26
(B) (C) (D) (E) (F)
02 01
13 03
30
13 0A "D" "V" "C"
13 06 "V" "E"
"J" "O" "P" " " "E"
"p" "o" "r" "a" "t"
13 05 "P" "L"
07 "D" "E" "V" "P"
13
15 13 08 "C" "P"
"P" "2" "5" "-" "2"
13 09 "P"
08 "C" "P" "U" "4"
"0" "-" "0" "N" 30
13 09 "P" "M"
"I" "O" "1" "0" "6"
"7" "N" "A" "M" "E"
"1" "P" "M"