Table of Contents
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P3
J15
VPP
P1
P2
U1
F326
RESET
Figure 3. CP250x Motherboard with Default Shorting Block Positions
Figure 4. CP2501 Development Daughter Board
PWR
J3
J7
VDD_DEBUG
VDD_PWR
+3VD
J1
J2
SILICON LABS
D10
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CP250x-MB
D11
D12
P5
CP2501-GM EDB
SILICON LABS
P3
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U1
CP
2501
J1
VBUS
VREGIN
VDD
Rev. 0.1
CP2501-DK
H1
GPIO7-0
J13
TB2
SMBUS_SDA
SMBUS_SCL
GND
TB1
UART_RX
UART_TX
GND
TB3
SPI_SCLK
SPI_MISO
SPI_MOSI
SPI_NSS
GND
GPIO15-8
H2
7
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