Processor 3/6 - Clevo NP50DB Service Manual

Processor 3/6

5
NEAR CPU
1.05V_VCCST
R34
100_04 56.2_1%_04
CPU
D
46 H_CPU_SVIDDAT
46 H_CPU_SVIDALRT#
46 H_CPU_SVIDCLK
220_04
46 H_PROCHOT#
44 DDR_VTT_PG_CTRL
R319 20_1%_04
26 H_PM_DOW N
TO PCH-H R322 CPU *12.1_1%_04
26 PCH_PECI
TO EC
R325 *0402_short
39 H_PECI
C
26 PCH_THERMTRIP#
CPU
CPU
VCCST_PWRGD
B
R336 0_04
22,25,39,46 ALL_SYS_PW RGD
CPU
C613
*0.1u_10V_X7R_04
CPU
G
39 H_PROCHOT_EC
A
R348
100K_04
CPU
5
4 3
U16E
R33 B31
29 PCH_CPU_BCLK_R_DP
BCLKP
A32
29 PCH_CPU_BCLK_R_DN BCLKN
CPU D35
29 PCH_CPU_PCIBCLK_R_DP
PCI_BCLKP
C36
29 PCH_CPU_PCIBCLK_R_DN
PCI_BCLKN
E31
29 CPU_24MHZ_R_DP
CLK24P
D31
29 CPU_24MHZ_R_DN
CLK24N
R35
CPU
VIDALERT# BH31
VIDALERT#
BH32
VIDSCK
BH29
VIDSOUT
H_PROCHOT#
R332 499_1%_04 PROCHOT# BR30
PROCHOT#
BT13
CPU
DDR_VTT_CNTL
Rubband
2019/12/17
CPU
VCCST_PW RGD VCCST_PW RGD_CPU
R326 60.4_1%_04 H13
VCCST_PWRGD
R681 10K_04 CPU
BT31
27 H_PW RGD
PROCPWRGD
BP35
26 PLTRST_CPU_N RESET# PROC_TDO
BM34
26 H_PM_SYNC PM_SYNC PROC_TDI
PM_DOW N
BP31
PM_DOWN PROC_TMS
BT34
PECI
PECI PROC_TCK
J31
THERMTRIP#
PROC_TRST#
H_SKTOCC_N
BR33
28,32 H_SKTOCC_N
SKTOCC# PROC_PREQ#
BN1
PROC_SELECT# PROC_PRDY#
C167
BM30
*0.1u_10V_X7R_04
CATERR#
CPU
CFG_RCOMP
AT13
ZVM#
AW13
MSM#
AU13
RSVD1
AY13
RSVD2
5 OF 13
CML_H_IP_EXT/BGA
1.05V_VCCST CPU
VDD3
R323
1K_04
CPU
VCCST_PW RGD
R324
100K_04
D
SYS_PW RGD#
2 G C609
CPU
S Q29A
*0.1u_10V_X7R_04
D MTDK3S6R CPU
CPU
5 G
S Q29B
MTDK3S6R
CPU
1.05DX_VCCSTG
H_PROCHOT#
R343 1K_04
CPU
Q32
C617
2SK3018S3 47p_25V_NPO_02
CPU CPU
CAD Note: Capacitor need to be placed
close to buffer output pin
24,25,27,30,32,33,34,36,38,39,40,41,42,43,46,47,49,50,51,52,53,54,55
4 3
2
Configuration Signals: The CFG signals have a
default value of '1' if not terminated on the board.
Refer to the appropriate platform design guide for
pull-down recommendations when a logic low is
desired.
CFG[0]: Stall reset sequence after PCU PLL
lock until de-asserted:
— 1 = (Default) Normal Operation; No
stall.
BN25 CFG0 CPU
T4 — 0 = Stall.
CFG_0 CFG_1
BN27 CPU
T3
CFG_1 CFG[1]: Reserved
BN26 CPU
CFG_2 CFG[2]: PCI Express* Static x16 Lane
BN28 CFG3 CPU
T2
CFG_3 Numbering Reversal.
BR20 CFG4 R354 1K_04 CPU
CFG_4 — 1 = Normal operation
BM20 R48 *1K_04
CFG_5
BT20 R349 *1K_04 — 0 = Lane numbers reversed.
CFG_6
BP20 CFG7 CPU CFG[3]: Reserved
T7
CFG_7
BR23 CFG8 CPU
CFG[4]: eDP
T57
CFG_8
BR22 CFG9 R346 *1K_04
— 1 = Disabled.
CFG_9
BT23 CPU
— 0 = Enabled.
CFG_10
BT22 CFG11 CPU
T58 CFG[6:5]: PCI
CFG_11
BM19
— 00 = 1 x8, 2 x4 PCI Express*
CFG_12
BR19
CPU
CFG_13 — 01 = reserved
BP19 CFG14
T61
CFG_14 — 10 = 2 x8 PCI Express*
BT19 CFG15
T62
CFG_15
— 11 = 1 x16 PCI Express*
CPU
BN23 CFG[7]: PEG
CPU
CFG_17
BP23 — 1 = (default) PEG Train immediately
CFG_16
BP22 following RESET# de assertion.
CFG_19
BN22
— 0 = PEG Wait for BIOS for training.
CFG_18
CFG[19:8]:
BR27
BPM#_0
BT27
BPM#_1
BM31
BPM#_2
BT30
BPM#_3
H_TDO
BT28
H_TDO 27
H_TDI
BL32
H_TDI 27
H_TMS
BP28
H_TMS 27
BR28 H_TCK
H_TCK 27
H_TRST#
BP30
H_TRST# 32
H_PREQ#
BL30
H_PREQ# 32
BP27 H_PRDY#
H_PRDY# 32
CFG_RCOMP
BT25
R43
49.9_1%_04
CPU
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
CFG2
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
DISPLAY PORT PRESENCE STRAP
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
CFG4
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
PCIE PORT BIFURCATION STRAPS
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5]
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
DEFENSIVE PULL DOWN SITE
CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
VDD3
6,26,42,46 1.05V_VCCST
Title Title Title
[04]Processor 3/6-CLK/JTAG/MISC [04]Processor 3/6-CLK/JTAG/MISC [04]Processor 3/6-CLK/JTAG/MISC
24,25,26,27,30,32,38,42,47 3.3VA
6,47 1.05DX_VCCSTG
Size Size Size Document Number Document Number Document Number
A3 A3 A3 N18P N18P N18P
Date: Date: Date: Monday, February 24, 2020 Monday, February 24, 2020 Monday, February 24, 2020
2
Schematic Diagrams
1
configuration lane.
D
configuration lane.
enable:
Express* Bifurcation
Training:
Reserved configuration lanes.
CPU
1.05DX_VCCSTG
CPU
H_TMS
R347 51_04
H_TDI
R37 51_04 C
Sheet 4 of 59
H_TDO
R333 100_04
CPU
H_TCK
R341 51_04
Processor 3/6
CPU
3.3VA
H_SKTOCC_N
R329 100K_04
CPU
B
A
R e v R e v R e v
6-71-NP500-D02 6-71-NP500-D02 6-71-NP500-D02
D02 D02 D02
Sheet Sheet Sheet 4 4 4 o f o f o f 59 59 59
1
Processor 3/6 B - 5