Clevo NP50DB Service Manual page 79

PCH 9/9
5
NO REBOOThis signal has an integrated weak BOOT STARP
pull-down resistor (20 KΩ nominal) to This signal has an integrated weak
disable the no reboot strap functionality pull-down resistor (20 KΩ
by default. to default boot from SPI.
To enable no reboot on TCO Timer To enable boot to LPC, this signal
expiration, this signal should be should be pulled up to V3.3S through
pulled-up to V3.3S through a 1k to 2.2 KΩ a 1k to 2.2 KΩ
± 5% resistor.
3.3VA
3.3VS
R153
D R176
*4.7K_04
*4.7K_04 PCH
LPSS_GSPI1_MOSI
LPSS_GSPI0_MOSI
3.3VS
GPIO
H: W / TPM
L: W/O TPM R131
10K_04
BIOS W / TPM
TPM_DET
R132
100K_04
W /O TPM
3.3VS
Leakage
C
SMI#_R
10K_04 R470
PCH
Psys=6.04K
120W
34,39 CNVI_DET#
PCH1.8VA
G61 G62
ID1 High Low
DEBUG BOT
R457
TX -> D+
10K_04
ID2 High Low
RX -> D-
PCH
GPP_J1 PCH
R494
Psys=19.6K
PCH R492
150W
G61 G62
ID1 Low High
PCH1.8VA
ID2 High Low
XTAL SELECT-1
HIGH -> 24 MHZ
LOW -> 38.4 MHZ
R121
B
4.7K_04 NP50 ID 100K_04
ID1 3.3VS
NP50 ID *100K_04
PCH
CNVI_BRI_DT
G61 ID 100K_04
ID2 3.3VS
G62 ID 100K_04
R119
24,28,39 SMI#
*10K_04
PCH Rubband
2019/12/23
4,28
Close to M.2
PCH1.8VA PCH1.8VA
34
M.2 CNVI STRAP PCH1.8VA R445 R453
HIGH -> DISABLE
LOW -> ENABLE
*20K_04 *20K_04
PCH PCH
34
R127
34 CNVI_BRI_RSP
34
20K_04
34 CNVI_RGI_RSP
PCH
34 CNVI_MFUART2_RXD
A 34 CNVI_MFUART2_TXD
CNVI_RGI_DT
Close to M.2
5
4 3
nominal)
± 5% resistor. ?
?
U27J
?
Y14
RSVD7
Y15
RSVD8
U37
RSVD6
U35
RSVD5
PCH
N32
RSVD3
R32
RSVD4
AH15
RSVD2
AH14
RSVD1
AL2
PREQ#
AM5
PRDY#
AM4
CPU_TRST#
PCH_2_CPU_TRIGGER_R
AK3
TRIGGER_OUT
AK2
TRIGGER_IN
10 OF 13
CML-H QS64
? PCH
?
?
U27K
?
LPSS_GSPI1_MOSI
BA26
GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
BD30
GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK
AU26
GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO
AW26
GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
LPSS_GSPI0_MOSI
BE30
GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN
BD29
GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
BF29
GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL
BB26
GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
R156 *0_04 BB24
GPP_C9/UART0A_TXD
BE23
GPP_C8/UART0A_RXD
AP24
PCH
GPP_C11/UART0A_CTS#
BA24
GPP_C10/UART0A_RTS#
GPP_H20/ISH_I2C0_SCL
BD21
GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
AW24
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AP21
GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL
AU24
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
AV21
GPP_C23/UART2_CTS#
AW21
UART2_TXD GPP_C22/UART2_RTS#
PCH *0_06 BE20
GPP_C21/UART2_TXD
UART2_RXD
*0_06 BD20
GPP_C20/UART2_RXD
PCH
BE21
GPP_C19/I2C1_SCL
BF21
GPP_C18/I2C1_SDA
BC22
37 I2C_SCL_TP GPP_C17/I2C0_SCL
BF23
37 I2C_SDA_TP GPP_C16/I2C0_SDA
BE15
GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4/BK4 GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BE14
GPP_D23/ISH_I2C2_SCL/I2C3_SCL
CML-H QS64 ?
11 OF 13
?
? PCH
U27M
BIOS
R130
?
R129
BOARD_ID1 CNV_WR_CLKN
AW13
BOARD_ID2 GPP_G0/SD_CMD CNV_WR_CLKP
BE9
GPP_G1/SD_DATA0
TPM_DET
R476 BF8
GPP_G2/SD_DATA1 CNV_WR_D0N
R477 BF9
18 GPIO4_1V8_MAIN_EN_R GPP_G3/SD_DATA2 CNV_WR_D0P
BG8
SMI#_R GPP_G4/SD_DATA3 CNV_WR_D1N
R690 0_04 BE8
GPP_G5/SD_CD# CNV_WR_D1P
BD8
GPP_G6/SD_CLK
PCH AV13
GPP_G7/SD_WP CNV_WT_CLKN
CNV_WT_CLKP
10K_04 R111 AP3
H_SKTOCC_N GPP_I11/M2_SKT2_CFG0
AP2
GPP_I12/M2_SKT2_CFG1 CNV_WT_D0N
PCH AN4
GPP_I13/M2_SKT2_CFG2 CNV_WT_D0P
AM7
GPP_I14/M2_SKT2_CFG3 CNV_WT_D1N
CNV_WT_D1P
AV6
CNVI_GNSS_PA_BLANKING GPP_J0/CNV_PA_BLANKING CNV_WT_RCOMP
AY3
42,47 GPP_J1 GPP_J1/CPU_C10_GATE#
AR13
75K_04 R126
GPP_J11/A4WP_PRESENT PCIE_RCOMPN
AV7
GPP_J10 PCIE_RCOMPP
100K_04 R458 AW3
GPP_J2 SD_1P8_RCOMP
100K_04 R116 AT10
GPP_J3 SD_3P3_RCOMP
22_04 R447 AV4
CNVI_BRI_DT GPP_J4/CNV_BRI_DT/UART0B_RTS# GPPJ_RCOMP_1P81
AY2
GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P82
22_04 R455 BA4
CNVI_RGI_DT GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P83
AV3
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
PCH AW2
GPP_J8/CNV_MFUART2_RXD
AU9
GPP_J9/CNV_MFUART2_TXD
PCH
PCH
13 OF 13
PCH
PCH
CML-H QS64
PCH
?
8,9,16,17,18,21,22,23,24,25,26,27,28,29,33,34,36,37,38,39,41,42,44,46
4,24,25,27,30,33,34,36,38,39,40,41,42,43,46,47,49,50,51,52,53,54,55
4 3
2
H_PREQ# 4
H_PRDY# 4
H_TRST# 4
R449 30.1_1%_04
PCH_2_CPU_TRIGGER 6
CPU_2_PCH_TRIGGER 6
PCH
BA20
BB20
BB16
AN18
BF14
AR18
BF17
BE17
AG45
AH46
AH47
AH48
PCH
DGPU_PW M_SELECT#
AV34
T22
GPP_A23/ISH_GP5
AW32
GPP_A22/ISH_GP4 SATA_PW R_EN 37
BA33 3G_CONFIG2
T20
GPP_A21/ISH_GP3
BE34
GPP_A20/ISH_GP2
BD34 PCH
GPP_A19/ISH_GP1
SB_BLON
BF35
GPP_A18/ISH_GP0 SB_BLON 22
BD38
BIOS
BD4
CNVI_W GR_CLKN 34
BE3
CNVI_W GR_CLKP 34
SB_BLON
BB3
CNVI_W GR_D0N 34
BB4
CNVI_W GR_D0P 34
BA3
CNVI_W GR_D1N 34
BA2
CNVI_W GR_D1P 34
BC5
CNVI_W T_CLKN 34
BB6
CNVI_W T_CLKP 34
BE6
CNVI_W T_D0N 34
BD7
CNVI_W T_D0P 34
BG6
CNVI_W T_D1N 34
BF6
CNVI_W T_D1P 34
CNV_W T_RCOMP
BA1 150_1%_04 R456 PCH
Differential between RCOMPN/RCOMPP.
B12 PCIECOMP_N
100_1%_04 R490 PCH
PCIECOMP_P Length matched to less than 1% trace.
A13
SD3_RCOMP_1P8
BE5 200_1%_04 R468
SD3_RCOMP_3P3
BE4 200_1%_04 R110
GPPJ_RCOMP_1P8
BD1 PCH
BE1
PCH
BE2 200_1%_04 R454
Y35 PCH
RSVD2
Y36
RSVD3
BC1
RSVD1
AL35
T24
TP
PCH
3.3VS Title Title Title
[32] PCH 10_11/12-UART/I2C/GPIO [32] PCH 10_11/12-UART/I2C/GPIO [32] PCH 10_11/12-UART/I2C/GPIO
4,24,25,26,27,30,38,42,47 3.3VA
VDD3
30 PCH1.8VA Size Size Size Document Number Document Number Document Number
A3 A3 A3 N18P N18P N18P
Date: Date: Date: Monday, February 24, 2020 Monday, February 24, 2020 Monday, February 24, 2020
2
Schematic Diagrams
1
D
Sheet 32 of 59
PCH 9/9
C
B
VDD3
R174 *10K_04
PCH
A
R e v R e v R e v
6-71-NP500-D02 6-71-NP500-D02 6-71-NP500-D02
D02 D02 D02
Sheet Sheet Sheet 32 32 32 o f o f o f 59 59 59
1
PCH 9/9 B - 33