Solder Bridges; Table 5. Solder Bridge Settings - ST STM32F0DISCOVERY User Manual

Discovery kit for stm32 f0 microcontrollers
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UM1525
4.8

Solder bridges

Table 5.
Solder bridge settings
Bridge
SB16,17
(2)
(X2 crystal)
SB6,8,10,12 (Default)
SB5,7,9,11 (Reserved)
SB20,21
(X3 crystal)
SB4
(B2-RESET)
SB3
(B1-USER)
SB1
(VBAT powered from VDD)
SB14,15
(RX,TX)
SB19
(NRST)
SB22
(T_SWO)
SB13
(STM_RST)
SB2
(BOOT0)
SB18
(2)
(MCO)
1. Default SBx state is shown in bold.
2. OSC_IN clock comes from MCO if SB18 is ON and SB16,17 are OFF
and comes from X2 if SB18 is OFF and SB16,17 are ON.
(1)
State
X2, C13, C14, R22 and R23 provide a clock. PF0, PF1 are disconnected
OFF
from P1.
ON
PF0, PF1 are connected to P1 (R22, R23 and SB18 must not be fitted).
ON
Reserved, do not modify.
OFF
Reserved, do not modify.
X3, C15, C16, R24 and R25 deliver a 32 KHz clock. PC14, PC15 are not
OFF
connected to P1.
ON
PC14, PC15 are only connected to P1 (R24, R25 must not be fitted).
B2 push button is connected to the NRST pin of the STM32F051R8T6
ON
MCU.
B2 push button is not connected the NRST pin of the STM32F051R8T6
OFF
MCU.
ON
B1 push button is connected to PA0.
OFF
B1 push button is not connected to PA0.
ON
VBAT is permanently powered from VDD.
OFF
VBAT is not powered from VDD but pin3 of P1.
OFF
Reserved, do not modify.
ON
Reserved, do not modify.
NRST signal of the CN3 connector is connected to the NRST pin of the
ON
STM32F051R8T6 MCU.
NRST signal of the CN3 connector is not connected to the NRST pin of the
OFF
STM32F051R8T6 MCU.
ON
SWO signal of the CN3 connector is connected to PB3.
OFF
SWO signal is not connected.
OFF
No incidence on STM32F103C8T6 (ST-LINK/V2) NRST signal.
ON
STM32F103C8T6 (ST-LINK/V2) NRST signal is connected to GND.
BOOT0 signal of the STM32F051R8T6 MCU is held low through a
ON
510 Ohm pull-down resistor.
BOOT0 signal of the STM32F051R8T6 MCU can be set high through a
OFF
10 KOhm pull-up resistor R27 to solder.
ON
Provides the 8 MHz for OSC_IN from MCO of STM32F103C8T6.
OFF
See SB16, SB17 description.
Doc ID 022910 Rev 2
Hardware and layout
Description
19/41

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