SIGNALCORE SC5511A Operating & Programming Manual page 44

Register writes are accomplished in a single write operation. Register buffer lengths vary depending on
the register; they vary in lengths of 2 to 6 bytes, with the first byte being the register address, followed
by the data associated with that register. The (����
1 ���� (T
see Figure 4) before data is clocked in, and must remain low for the entire register write. The
S,
clock rate may be as high as 5.0 MHz (T
sufficient integrity due trace issues, the rate should be lowered.
T T
S C
CLK
DATA 8 Bit Command/ Reg. Address
CS
Figure 4 SPI timing.
As mentioned above, the SPI architecture limits the byte rate due to the fact that after every byte
transfer the input and output SPI buffers need to be cleared and loaded respectively by the device SPI
engine. Data is transferred between the buffers and the internal registers. The time required to perform
this task is indicated by ��
beginning of another. The recommended minimum time delay for ��
transferred depends on the register. It is important that the correct number of bytes is transferred for
the associated device register, because once the first byte (MSB) containing the device register address
is received, the device will wait for the desired number of associated data bytes. The device will hang if
an insufficient number of bytes are written to the register. In order to clear the hung condition, the
device will need an external hard reset. The time required to process a command is also dependent on
the command itself. Measured times for command completions are between 50 ���� to 600 ���� after
reception. To change the frequency with auto leveling turned on requires the most computational time.
The computational time to change frequencies is approximately 250 ���� and to computational time to
change power level is approximately 350 ����.
Writing the SPI Bus
The SPI transfer size (in bytes) depends on the register being targeted. The MSB byte is the command
register address as noted in the Setting the SC5511A: Configuration Registers section. The subsequent
bytes contain the data associated with the register. As data from the host is being transferred to the
device via the SDI (MOSI) line, data present on its SPI output buffer is simultaneously transferred back,
MSB first, via the SDO (MISO) line.
SC5511A User Manual
̅ ̅ ̅̅ ) pin must be asserted low for a minimum period of
= 0.2 ����), however if the external SPI signals do not have
C
T
B
, which is the time interval between the end of one byte transfer and the
��
Byte N (MSB)
��
Rev 1.7.0
Byte N-1 (LSB)
is 1 ����. The number of bytes
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