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ON Semiconductor NCP45491PMNGEVB User Manual

Paired mode evaluation board
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NCP45491PMNGEVB
NCP45491 Paired Mode
Evaluation Board User's
Manual
Introduction
This user's manual provides detailed information
regarding
the
configuration
NCP45491PMNGEVB evaluation board. The evaluation
board serves as a demonstration of NCP45491 general
functionality for dual mode chip mode featuring power
monitoring of 6 channels. The evaluation board also
provides a means of quick prototyping for specific
applications.
Features
2 NCP45491 Connected in Paired Mode
Connectors for 6 High Current Loads and 3 Separate Bus
Voltage Supplies
Configuration Options for Shunt Current and Bus Voltage
Gain Settings
Appropriate Test Points for Easy Evaluation
Quick Start
Recommended Equipment
Before beginning, the following equipment is needed:
4 DC Power Supplies (3.3 V VCC Supply, 12 V Bus
Voltage, 6 V Bus Supply, 8 V Bus Supply)
6 DC loads (Up to at Least 2 A)
1 Function Generator
1 Oscilloscope
1 Digital Multi-meter
SMA to BNC Cables Recommended for Connection to
DIFF_OUTN, DIFF_OUTP, and MUX_SEL
NOTE: Bus voltage supplies need to be capable of
sourcing load currents times 2 since each supply
sources 2 loads on the default setup.
Board Setup
The assembled evaluation board targets Bus Voltages and
Shunt Currents shown in Tables 1 and 2. VBUS1 ties to both
channel 1 and channel 2 bus voltage inputs. VBUS2 ties to
both channel 3 and channel 4 bus voltage inputs. VBUS3 ties
to both channel 5 and channel 6 bus voltage inputs. Refer to
the schematic and layout diagrams found in
Appendix B
respectively as needed.
© Semiconductor Components Industries, LLC, 2018
December, 2018 − Rev. 0
and
use
of
the
Appendix A
and
1
www.onsemi.com
EVAL BOARD USER'S MANUAL
Table 1. BUS VOLTAGE SETUP
Channel
Target Bus Voltage
1 (VBUS1)
2 (VBUS1)
3 (VBUS2)
4 (VBUS2)
5 (VBUS3)
6 (VBUS3)
Table 2. SHUNT CURRENT SETUP
Shunt Current
Target
Channel
Load 1
Load 2
Load 3
Load 4
Load 5
Load 6
The specific resistor configuration populated on the board
facilitates these gain settings. The nominal differential
amplifier gain is 2 V/V. Therefore, the expected differential
output for any channels voltage or current can be calculated
as follows:
For Bus Voltage:
Diff Output = Bus Voltage × Channel Bus Divider × 2
For Load Current:
Diff Output = Load Current × Channel Shunt Gain × 2
The output for each channel is calculated as follows:
Diff Output + Bus Voltage
The channel shunt current gain is calculated as follows:
Diff Output + I
load
Bus Divider
12 V
1/60 V/V
12 V
1/60 V/V
6 V
1/30 V/V
6 V
1/30 V/V
8 V
1/40 V/V
8 V
1/40 V/V
Shunt Gain
Default Setting
1 A
400 mV/A
0.5 A
400 mV/A
1 A
400 mV/A
0.5 A
400 mV/A
1 A
400 mV/A
0.5 A
400 mV/A
R4
(eq. 1)
2
R4 ) R3
R2
R
sense
(eq. 2)
2
R1
Publication Order Number:
EVBUM2592/D

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Summary of Contents for ON Semiconductor NCP45491PMNGEVB

  • Page 1 This user’s manual provides detailed information EVAL BOARD USER’S MANUAL regarding configuration NCP45491PMNGEVB evaluation board. The evaluation board serves as a demonstration of NCP45491 general functionality for dual mode chip mode featuring power Table 1. BUS VOLTAGE SETUP monitoring of 6 channels. The evaluation board also...
  • Page 2 NCP45491PMNGEVB These gain settings can be adjusted by changing the bus Make all board connections with supplies and loads divider resistors, and the shunt current network resistors as disabled. Take adequate precautions when working with desired. high current and high voltage applications. Table 3 below defines all default board connections and their purpose.
  • Page 3 NCP45491PMNGEVB Testing Procedure PCB Layout The NCP45491PMNGEVB comes fully assembled and Care must be taken in PCB layout regarding a few specific tested. Follow the steps below to verify board operation. nodes for proper operation of the NCP45491. Connections Refer to the schematic and layout diagrams found in...
  • Page 4 NCP45491PMNGEVB APPENDIX A: NCP45491 PAIRED MODE EVALUATION BOARD SCHEMATIC 100K SKIP MUX_SEL BS_OK BS_OK MUX_SEL MUX_SEL 100K DIFF_OUTP BS_REF BS_REF SH_IN_N1 SH_IN_N1 BS_REF SH_IN_N4 SH_IN_N1 BS_REF DIFF_OUT_P SH_IN_P1 SH_IN_P1 BG_REF_OUT SH_IN_P4 SH_IN_P1 BG_REF_OUT CM_REF_IN CM_REF_IN BS_IN1 BS_IN1 CM_REF_IN BS_IN4 BS_IN1...
  • Page 5: Appendix B: Bill Of Materials

    NCP45491PMNGEVB APPENDIX B: BILL OF MATERIALS Table 5. BILL OF MATERIALS Designator Description Value Manufacturer Manufacturer P/N Footprint BG_REF_OUT, BS_IN1, BS_IN2, Test Points Keystone Electronics 5009 Test_Point BS_IN3, BS_IN4, BS_IN5, BS_IN6, BS_OK, BS_REF, CM_REF_IN, DIFF_OUTN, DIFF_OUTP, GND1, GND2, GND3, GND4, GND5, SH_IN1,...
  • Page 6 NCP45491PMNGEVB APPENDIX C: NCP45491 EVALUATION BOARD LAYOUT Figure 2. PCB Front (Top Metallization) www.onsemi.com...
  • Page 7 NCP45491PMNGEVB Rsense1 Rsense2 Rsense3 Rsense4 Rsense5 Rsense6 Figure 3. PCB Backside (Bottom Metallization) www.onsemi.com...
  • Page 8: Technical Support

    LIMITATIONS OF LIABILITY: ON Semiconductor shall not be liable for any special, consequential, incidental, indirect or punitive damages, including, but not limited to the costs of requalification, delay, loss of profits or goodwill, arising out of or in connection with the board, even if ON Semiconductor is advised of the possibility of such damages. In no event shall ON Semiconductor’s aggregate liability from any obligation arising out of or in connection with the board, under any theory of liability, exceed the purchase price paid for the board, if any.