Maxim Integrated MAX32665 User Manual

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MAX32665–MAX32668 USER GUIDE

UG6971; Rev 0; 6/19

Abstract:

This user guide provides application developers information on how to use the memory and peripherals of the

MAX32665–MAX32668 microcontroller. Detailed information for all registers and fields in the device are covered.

Guidance is given for managing all the peripherals, clocks, power and startup for the device family.

Table of Contents

Summary of Contents for Maxim Integrated MAX32665

Page 1 This user guide provides application developers information on how to use the memory and peripherals of the MAX32665–MAX32668 microcontroller. Detailed information for all registers and fields in the device are covered. Guidance is given for managing all the peripherals, clocks, power and startup for the device family.
Page 2: Table Of Contents
MAX32665-MAX32668 User Guide MAX32665—MAX32669 User Guide Table of Contents Overview ----------------------------------------------------------------------------------------------------------------- 24 Block Diagram ---------------------------------------------------------------------------------------------------------------- 25 Resource Protection Unit (RPU) ------------------------------------------------------------------------------------ 26 Instances ----------------------------------------------------------------------------------------------------------------------- 26 Usage --------------------------------------------------------------------------------------------------------------------------- 28 2.2.1 Reset State -------------------------------------------------------------------------------------------------------------------------------- 28 2.2.2 MPU Implementation ------------------------------------------------------------------------------------------------------------------ 28 2.2.3 MPU Protection Fault ------------------------------------------------------------------------------------------------------------------ 28 2.2.4...
Page 3 MAX32665-MAX32668 User Guide 3.4.1 Core AHB Interfaces --------------------------------------------------------------------------------------------------------------------- 40 3.4.2 AHB Masters ------------------------------------------------------------------------------------------------------------------------------ 41 Peripheral Register Map --------------------------------------------------------------------------------------------------- 41 3.5.1 APB Peripheral Base Address Map -------------------------------------------------------------------------------------------------- 41 3.5.2 AHB Peripheral Base Address Map ------------------------------------------------------------------------------------------------- 42 Error Correction Coding (ECC) Module --------------------------------------------------------------------------------- 43 3.6.1...
Page 4 MAX32665-MAX32668 User Guide RAM Memory Management ---------------------------------------------------------------------------------------------- 67 4.8.1 RAM Zeroization ------------------------------------------------------------------------------------------------------------------------- 67 4.8.2 RAM Low Power Modes --------------------------------------------------------------------------------------------------------------- 67 Miscellaneous Control Registers ----------------------------------------------------------------------------------------- 68 4.10 Miscellaneous Control Registers Details ------------------------------------------------------------------------------- 68 4.11 Single Inductor Multiple Output (SIMO) Power Supply ------------------------------------------------------------ 71 4.11.1...
Page 5 MAX32665-MAX32668 User Guide 7.2.1 Clock Configuration ------------------------------------------------------------------------------------------------------------------- 135 7.2.2 Lock Protection ------------------------------------------------------------------------------------------------------------------------- 135 7.2.3 Flash Write Width --------------------------------------------------------------------------------------------------------------------- 135 7.2.4 Flash Write ------------------------------------------------------------------------------------------------------------------------------ 136 7.2.5 Page Erase ------------------------------------------------------------------------------------------------------------------------------- 136 7.2.6 Mass Erase ------------------------------------------------------------------------------------------------------------------------------ 137 Flash Error Correction Coding ------------------------------------------------------------------------------------------ 137...
Page 6 MAX32665-MAX32668 User Guide 9.2.3 Data Movement From the DMA to Destination ------------------------------------------------------------------------------- 226 Usage ------------------------------------------------------------------------------------------------------------------------- 227 Count-To-Zero (CTZ) Condition ---------------------------------------------------------------------------------------- 227 Chaining Buffers ----------------------------------------------------------------------------------------------------------- 228 DMA Interrupts ------------------------------------------------------------------------------------------------------------ 230 Channel Timeout Detect ------------------------------------------------------------------------------------------------- 230 Memory-to-Memory DMA ---------------------------------------------------------------------------------------------- 231 DMAC Registers ------------------------------------------------------------------------------------------------------------ 231 9.10...
Page 7 MAX32665-MAX32668 User Guide 12.1 Instances --------------------------------------------------------------------------------------------------------------------- 260 12.2 UART Frame ----------------------------------------------------------------------------------------------------------------- 260 12.3 UART Interrupts ------------------------------------------------------------------------------------------------------------ 261 12.4 UART Baud Rate Clock Source ------------------------------------------------------------------------------------------ 261 12.5 UART Baud Rate Calculation -------------------------------------------------------------------------------------------- 261 12.6 UART Configuration and Operation ----------------------------------------------------------------------------------- 263 12.7 Wakeup Time --------------------------------------------------------------------------------------------------------------- 263 12.8...
Page 8 MAX32665-MAX32668 User Guide 13.6 Register Details ------------------------------------------------------------------------------------------------------------ 293 Quad Serial Peripheral Interface (SPI) ------------------------------------------------------------------------- 306 14.1 Instances --------------------------------------------------------------------------------------------------------------------- 307 14.2 SPI Formats ----------------------------------------------------------------------------------------------------------------- 308 14.2.1 Four-Wire SPI --------------------------------------------------------------------------------------------------------------------------- 308 14.2.2 Three-Wire SPI -------------------------------------------------------------------------------------------------------------------------- 309 14.3 Pin Configuration ---------------------------------------------------------------------------------------------------------- 310 14.3.1 QSPIn Alternate Function Mapping ----------------------------------------------------------------------------------------------- 310 14.3.2...
Page 9 MAX32665-MAX32668 User Guide 16.3 Timer Pin Functionality--------------------------------------------------------------------------------------------------- 330 16.4 One-Shot Mode (000b) --------------------------------------------------------------------------------------------------- 330 16.4.1 One-Shot Mode Timer Period ------------------------------------------------------------------------------------------------------ 331 16.4.2 One-Shot Mode Configuration ----------------------------------------------------------------------------------------------------- 331 16.5 Continuous Mode (001b) ------------------------------------------------------------------------------------------------ 331 16.5.1 Continuous Mode Timer Period ---------------------------------------------------------------------------------------------------- 332 16.5.2...
Page 10 MAX32665-MAX32668 User Guide 17.7 Pulse Train Interrupts ---------------------------------------------------------------------------------------------------- 352 17.8 Registers --------------------------------------------------------------------------------------------------------------------- 352 17.9 Register Details ------------------------------------------------------------------------------------------------------------ 354 17.9.1 Pulse Train Engine Safe Enable Register ----------------------------------------------------------------------------------------- 363 17.9.2 Pulse Train Engine Safe Disable Register ---------------------------------------------------------------------------------------- 364 Real-Time Clock (RTC) --------------------------------------------------------------------------------------------- 369 18.1...
Page 11 MAX32665-MAX32668 User Guide 20.1 Instances --------------------------------------------------------------------------------------------------------------------- 387 20.2 Pins and Configuration --------------------------------------------------------------------------------------------------- 388 20.2.1 Pin Configuration ---------------------------------------------------------------------------------------------------------------------- 388 20.2.2 1-Wire I/O (OWM_IO) ---------------------------------------------------------------------------------------------------------------- 388 20.2.3 Pullup Enable (OWM_PE) ----------------------------------------------------------------------------------------------------------- 388 20.2.4 Clock Configuration ------------------------------------------------------------------------------------------------------------------- 388 20.3 1-Wire Protocol ------------------------------------------------------------------------------------------------------------ 389 20.3.1...
Page 12 MAX32665-MAX32668 User Guide 21.10 Isochronous Endpoints --------------------------------------------------------------------------------------------------- 407 21.10.1 Isochronous IN Endpoints ------------------------------------------------------------------------------------------------------- 407 21.10.2 Isochronous OUT Endpoints ---------------------------------------------------------------------------------------------------- 408 21.11 USBHS Device Registers -------------------------------------------------------------------------------------------------- 409 21.12 USBHS Device Register Details ----------------------------------------------------------------------------------------- 410 21.12.2 Endpoint Register Access Control --------------------------------------------------------------------------------------------- 416 21.12.3...
Page 13 Figure 16-5: Counter Mode Diagram ............................340 Figure 16-6: Gated Mode Diagram ............................342 Figure 18-1. MAX32665―MAX32668 RTC Block Diagram (12-bit Sub-Second Counter) ............369 Figure 18-2. RTC Busy/Ready Signal Timing ..........................371 Figure 18-3. RTC Interrupt/Wakeup Diagram Wakeup Function ..................... 373 Figure 18-4.
Page 14 Figure 20-3: 1-Wire Write Time Slot ............................391 Figure 20-4: 1-Wire Read Time Slot ............................391 Figure 20-5: 1-Wire ROM ID Fields ............................392 Figure 22-1: MAX32665—MAX32668 Bluetooth Stack Overview ................... 427 Figure 23-1. Cryptographic Accelerator Block Diagram ......................430 Figure 23-2. DMA Block Diagram ............................. 431 Figure 23-3.
Page 15 Table 2-2. MAX32665—MAX32668 Master Permission Bits ..................... 26 Table 2-3: MAX32665—MAX32668 AHB Slaves ........................27 Table 2-4. MAX32665—MAX32668 AHB Master/Slave Interconnect Matrix ................27 Table 2-5: RPU APB Register Offsets, Names, Access, and Descriptions ................... 29 Table 2-6: RPU AHB Slave Register Addresses, Names, Access, and Descriptions ..............30 Table 2-7: RPU APB Slave Permission Registers .........................
Page 16 Table 5-1: MAX32665—MAX32668 Interrupt Vector Table ....................115 Table 6-1: MAX32665—MAX32668 GPIO Pin Count ....................... 119 Table 6-2: MAX32665—MAX32668 GPIO and Alternate Function Matrix, 140 WLP .............. 120 Table 6-3: MAX32665—MAX32668 GPIO Pin Configuration ....................121 Table 6-4: MAX32665—MAX32668 Input Mode Configuration ....................121 Table 6-5: MAX32665—MAX32668 Output Mode Configuration ...................
Page 17 Table 6-41: GPIOn Pulldown/Pullup Strength Select Register ....................133 Table 6-42: GPIOn Supply Voltage Select Register ........................133 Table 7-1: MAX32665—MAX32668 Internal Flash Memory Organization ................134 Table 7-2: Valid Addresses Flash Writes ..........................135 Table 7-3: Flash Controller Registers ............................137 Table 7-4: Flash Controller Address Pointer Register ......................
Page 18 Table 8-41: SRCC Cache Control Register ..........................179 Table 8-42: SRCC Invalidate Register ............................180 Table 8-43: MAX32665—MAX32668 SDHC Alternate Function Mapping to SDHC Specification Pin Names ......182 Table 8-44: Registers Used to Generate SD Commands ......................184 Table 8-45: SDHC Register Offsets, Names and Descriptions ....................185 Table 8-46: SDHC SDMA System Address / Argument Register....................
Page 19 Table 8-95: SDHC Host Controller Version Register ......................... 221 Table 9-1: MAX32665—MAX32668 DMAC and Channel Instances ..................223 Table 9-2: MAX32665—MAX32668 DMAC Source and Destination by Peripheral ..............224 Table 9-3: Data Movement from Source to DMA FIFO ......................226 Table 9-4: Data Movement from the DMA FIFO to Destination ....................
Page 20 Table 10-10: CRC Value Register .............................. 245 Table 10-11: CRC Pseudo-Random Number Generator Register ..................... 245 Table 11-1: MAX32665—MAX32668 ADC Peripheral Pins ...................... 246 Table 11-2: ADC Clock Frequency and ADC Conversion Time (�� = 96��, �� = 48��)......249 Table 11-3: Input and Reference Scale Support by ADC Input Channel ..................
Page 21 Table 17-10: Pulse Train n Loop Configuration Register ......................367 Table 17-11: Pulse Train n Automatic Restart Configuration Register ..................367 Table 18-1. MAX32665―MAX32668 RTC Counter and Alarm Registers ................. 370 Table 18-2. RTC Register Access .............................. 370 Table 18-3. MAX32665―MAX32668 RTC Square Wave Output Configuration ..............374 Table 18-4.
Page 22 MAX32665-MAX32668 User Guide Table 18-7. RTC Time-of-Day Alarm Register ........................... 377 Table 18-8. RTC Sub-Second Alarm Register ..........................377 Table 18-9. RTC Control Register ............................. 377 Table 18-10. RTC 32KHz Oscillator Digital Trim Register ......................379 Table 18-11. RTC 32KHz Oscillator Control Register ........................ 379 Table 19-1: Watchdog Timer Interrupt Period fSYS_CLK = 96MHz and fPCLK = 48MHz ............
Page 23 MAX32665-MAX32668 User Guide Table 23-2. Symmetric Block Ciphers ............................433 Table 23-3. Hash Functions ..............................436 Table 23-4. Cryptographic Memory Segments ........................440 Table 23-5. MAA Memory Segments and Locations ........................ 441 Table 23-6. MAA Memory Blinding Example (Memory Instance 0, MAWS > 1024) ..............441 Table 23-7.
Page 24: Overview
MAX32665-MAX32668 User Guide Overview The MAX32665–MAX32668 are Arm® Cortex®-M4 with FPU-based microcontrollers with 1MB flash and up to 560KB SRAM that can be configured as 448KB SRAM with error correction coding (ECC). They are ideal for wearable medical fitness applications. Optionally available is a second Arm Cortex-M4 with FPU for audio signal processing in a wireless headset/earbud application (MAX32665/MAX32666 only).
Page 25: Block Diagram
MAX32665-MAX32668 User Guide Block Diagram Figure 1-1: MAX32665—MAX32668 Block Diagram MAX32665/MAX32666/MAX32667/MAX32668 SD3.0/S DIO3.0/ 96MHz Arm® Cortex®-M4 eMMC4.51 HOST WITH FPU CPU0 60MHz 96MHz HFXOUT NVIC 3 × I C MASTER HFXIN 32 .768kHz Arm® Cortex®-M4 WITH FPU CPU1 7.3728MHz 3 × 4-WIRE UART...
Page 26: Resource Protection Unit (Rpu)
Because of the structure of the APB bus, there is only one access control bit. This means that the read and write access permissions for a particular master must always be the same. Access permissions for read and write can be configured separately for AHB slaves. Table 2-2. MAX32665—MAX32668 Master Permission Bits Bit Position in SLAVEAPB Register Bit Position in...
Page 27: Table 2-3: Max32665-Max32668 Ahb Slaves
System RAM, Memory Instance 6 The AHB bus prohibits some AHB master and slave interactions as shown in Table 2-4. The AHB slave ignores the state of prohibited combinations. Table 2-4. MAX32665—MAX32668 AHB Master/Slave Interconnect Matrix AHB Slave AHB Master DMAC0 DMAC1 SYS0...
Page 28: Usage
MAX32665-MAX32668 User Guide SPIM USBHS Data Cache SDIO/SDHC Target QSPI/SPI Usage 2.2.1 Reset State During a power-on-reset event, RPU registers are reset to their reset value. If RPU protection is desired, the registers must be reprogrammed during the boot sequence.
Page 29: Registers
MAX32665-MAX32668 User Guide Registers Table 3-1: APB Peripheral Base Address Map for the RPU Peripheral Base Address. Table 2-5: RPU APB Register Offsets, Names, Access, and Descriptions Offset Register Access Description [0x0000] GCR RPU Register [0x0004] SIR RPU Register [0x0008]...
Page 30: Table 2-6: Rpu Ahb Slave Register Addresses, Names, Access, And Descriptions
MAX32665-MAX32668 User Guide Offset Register Access Description [0x0270] SPIXFC SPIXFC RPU Register [0x0280] DMA0 DMA0 RPU Register [0x0290] FLC0 FLC0 RPU Register [0x0294] FLC1 FLC1 RPU Register [0x02A0] ICC0 ICC0 RPU Register [0x02A4] ICC1 ICC1 RPU Register [0x02F0] ICX RPU Register...
Page 31: Register Details
MAX32665-MAX32668 User Guide APB Address Register Access Description [0x0F00] SYS_RAM (MI0) SYS_RAM (MI0) RPU Register [0x0F10] SYS_RAM (MI1) SYS_RAM (MI1) RPU Register [0x0F20] SYS_RAM (MI2) SYS_RAM (MI2) RPU Register [0x0F30] SYS_RAM (MI3) SYS_RAM (MI3) RPU Register [0x0F40] SYS_RAM (MI4) SYS_RAM (MI4) RPU Register...
Page 32 MAX32665-MAX32668 User Guide Register Name Register Mnemonic Reference Timer 4 RPU Register TMR4 Table 2-5 Timer 5 RPU Register TMR5 Table 2-5 HTimer 0 RPU Register HTMR0 Table 2-5 HTMR1 Table 2-5 HTimer 1 RPU Register I2C Bus 0 (Bus 0) RPU Register...
Page 33: Table 2-8: Rpu Ahb Slave Permission Register
MAX32665-MAX32668 User Guide Register Name Register Mnemonic Reference I2C 0 (Bus 1) RPU Register I2C0_BUS1 Table 2-5 I2C 1 (Bus 1) RPU Register I2C1_BUS1 Table 2-5 I2C 2 (Bus 1) RPU Register I2C2_BUS1 Table 2-5 PTG_BUS1 Table 2-5 Pulse Train Engine (Bus 1) RPU Register...
Page 34: Memory, Register Mapping, And Access
MAX32665-MAX32668 User Guide Memory, Register Mapping, and Access Memory, Register Mapping, and Access Overview The Arm Cortex-M4 architecture defines a standard memory space for unified code and data access. This memory space is addressed in units of single bytes but is most typically accessed in 32-bit (4 byte) units. It may also be accessed, depending on the implementation, in 8-bit (1 byte) or 16-bit (2 byte) widths.
Page 35: Figure 3-1: Code Memory Mapping
MAX32665-MAX32668 User Guide Figure 3-1: Code Memory Mapping Legend Arm Cort ex-M4 Defined Buses Memory Spaces Memory Spaces (Cached) External Memory Device (Optional) 0xFFFF_FFFF Int ernal Memory I nstances Undefined/Reserved Reserved 0xA000_0000 0x9FFF_FFFF 0x9FFF_FFFF I-Code A ccess to Co de Sp ace...
Page 36: Figure 3-2: Data Memory Mapping
MAX32665-MAX32668 User Guide Figure 3-2: Data Memory Mapping Le gend 0x40 13_C000 Pulse Tra in s - BUS 1 0x4012_0000 Reserved ARM Cort ex-M4 AHB Bus Mast ers AHB Bus Masters 0x40 11_D000 I2C (0, 1, 2) – BUS 1...
Page 37: Standard Memory Regions
The code space memory on the MAX32665—MAX32668 also contains the mapping for the flash information block, from 0x1080 0000 to 0x1080 7FFF. However, this mapping is generally only present during Maxim Integrated production test; it is disabled once the information block has been loaded with valid data and the info block lockout option has been set. This memory is accessible for data reads only and cannot be used for code execution.
Page 38: Peripheral Space
AHB bus error. The SRAM area on the MAX32665—MAX32668 can be used to contain executable code. Code stored in the SRAM is accessed directly for execution (using the system bus) and is not cached. The SRAM is also where the Arm Cortex-M4 stack must be located, as it is the only general-purpose SRAM memory on the device.
Page 39: External Device Space
The external device space area of memory is intended for use in mapping off-chip device control functions onto the AHB bus. This memory space is defined from byte address range 0xA000 0000 to 0xDFFF FFFF (1GB maximum). The MAX32665— MAX32668 does not implement this memory area.
Page 40: External Memory Cache Controller (Emcc)
TPU Memory The MAX32665—MAX32668 contains a specialized 128-bit memory that is designed to preserve critical data (such as a 128- bit AES key) even when the device is in the lowest power-saving state. As long as the RTC power supply is still available, the contents of this memory will be retained, even if the AES block and the main SRAM are shut down completely.
Page 41: Ahb Masters
MAX32665-MAX32668 User Guide 3.4.2 AHB Masters 3.4.2.1 USB Endpoint Buffer Manager The USB AHB bus master is used to manage endpoint buffers in the SRAM. It has access to the SRAM (read/write, for storage and retrieval of endpoint buffer data), as well as the internal and/or external flash data contents (which can be used to contain static data for transmission by the USB).
Page 42: Ahb Peripheral Base Address Map
MAX32665-MAX32668 User Guide Peripheral Register Name Register Prefix APB Base Address APB End Address Timer 1 TMR1_ 0x4001 1000 0x4001 1FFF Timer 2 TMR2_ 0x4001 2000 0x4001 2FFF Timer 3 TMR3_ 0x4001 3000 0x4001 3FFF Timer 4 TMR4_ 0x4001 4000...
Page 43: Error Correction Coding (Ecc) Module
MAX32665-MAX32668 User Guide Table 3-2: AHB Peripheral Base Address Map AHB Peripheral Register Name Register Prefix AHB Base Address AHB End Address USB Hi-Speed Host USBHS_ 0x400B 1000 0x400B 1FFF SDIO/SDHC Controller (AHB) SDHC_ 0x400B 6000 0x400B 6FFF SPIXF Master Controller FIFO...
Page 44: Table 3-3: Error Correction Coding (Ecc) Enable Register
MAX32665-MAX32668 User Guide Table 3-3: Error Correction Coding (ECC) Enable Register Error Correction Coding Enable GCR_ECC_EN [0x6C00] Bits Field Access Reset Description 31:13 Reserved for Future Use Do not modify this field. fl1eccen Flash1 ECC Enable 0: Disable 1: Enable...
Page 45 MAX32665-MAX32668 User Guide Error Correction Coding Error GCR_ECC_ER [0x0064] Bits Field Access Reset Description fl1eccerr R/W1C ECC Flash1 Error Indicates an ECC error in the Flash1 bank. Write to 1 to clear. 0: No Error 1: Error fl0eccerr R/W1C ECC Flash0 Error Indicates an ECC error in the Flash0 bank.
Page 46: Table 3-5: Correctable Error Detected Register
MAX32665-MAX32668 User Guide Table 3-5: Correctable Error Detected Register Correctable Error Detected GCR_ECC_CED [0x0068] Bits Field Access Reset Description 31:13 Reserved for Future Use Do not modify this field. fl1eccnded R/W1C ECC Flash1 Correctable Error Detected Indicates a single bit correctable error in the Flash1 bank. Write to 1 to clear.
Page 47: Table 3-6: Error Correction Coding (Ecc) Interrupt Enable Register
MAX32665-MAX32668 User Guide Correctable Error Detected GCR_ECC_CED [0x0068] Bits Field Access Reset Description sysram1ecc_ced R/W1C ECC Sysram1 Correctable Error Detected Indicates a single bit correctable error in the Sysram 1 block. Write to 1 to clear. 0: No single bit error detected...
Page 48: Table 3-7: Error Correction Coding (Ecc) Address Register
MAX32665-MAX32668 User Guide Error Correction Coding Interrupt Enable GCR_ECC_IRQEN [0x006C] Bits Field Access Reset Description sysram4irqen ECC Sysram4 Interrupt Enable When set, indicates that the interrupt is enabled for occurrence upon a detected error in the Sysram4 block if GCR_ECC_EN.sysram4en is set.
Page 49 MAX32665-MAX32668 User Guide Error Correction Coding Address GCR_ECC_ERRAD [0x0070] Bits Field Access Reset Description dataramerr ECC Error Address/DATA RAM Error Address Data depends on which block has reported the error. If sysram, fl0, or fl1, then this bit(s) represents bit 15 of the AMBA address of read which produced the error.
Page 50: System, Power, Clocks, Reset
MAX32665-MAX32668 User Guide System, Power, Clocks, Reset There are several clocks used by different peripherals and subsystems. These clocks are highly configurable by firmware, allowing developers to select the combination of application performance and power savings required for the target systems.
Page 51: Figure 4-1: Clock Block Diagram
MAX32665-MAX32668 User Guide Figure 4-1: Clock Block Diagram Maxim Integrated Page 51 of 457...
Page 52: Oscillator Inplementation
MAX32665-MAX32668 User Guide 4.1.1 Oscillator Inplementation Before using any oscillator, the desired oscillator must first be enabled by setting the oscillator’s enable bit in the GCR_CLK_CTRL register. Once an oscillator’s enable bit is set, the oscillator’s ready bit must read 1 prior to attempting to use the oscillator as a system oscillator source.
Page 53: 8Mhz Internal Oscillator
MAX32665— MAX32668 HFXIN The crysta l lo ad, C , as specified in the MAX32665-MAX 32668 datasheet Electrical HFXIN STRAYIN Characteristics Ta ble is req uired to b e 12 pF. Th ere fore, th e tota l ca pacitance se en...
Page 54: Operating Modes
MAX32665-MAX32668 User Guide Operating Modes The MAX32665—MAX32668 provides four operating modes: • ACTIVE • SLEEP • DEEPSLEEP • BACKUP ACTIVE is the highest performance operating mode. Any low power state can wake up to ACTIVE by a wakeup event shown Table 4-1.
Page 55: Figure 4-3: Sleep Mode Clock Control
MAX32665-MAX32668 User Guide Figure 4-3: SLEEP Mode Clock Control Maxim Integrated Page 55 of 457...
Page 56: Deepsleep Low Power Mode
MAX32665-MAX32668 User Guide 4.2.3 DEEPSLEEP Low Power Mode All internal clocks, except the 8kHz, are gated off. SYS_OSC is gated off, so the two main bus clocks PCLK and HCLK are inactive. The CPU state is retained. The 32kHz oscillator can be enabled via firmware.
Page 57: Figure 4-4: Deepsleep Clock Control
MAX32665-MAX32668 User Guide Figure 4-4: DEEPSLEEP Clock Control Maxim Integrated Page 57 of 457...
Page 58: Backup Low Power Mode
MAX32665-MAX32668 User Guide 4.2.4 BACKUP Low Power Mode This is the lowest power operating mode. All oscillators are disabled except for the 8kHz and the 32kHz oscillator. The 32kHz oscillator is firmware controlled. SYS_OSC is gated off, so PCLK and HCLK are inactive. The CPU state is not maintained.
Page 59: Figure 4-5: Backup Mode Clock Control
MAX32665-MAX32668 User Guide Figure 4-5: BACKUP Mode Clock Control Maxim Integrated Page 59 of 457...
Page 60: Device Resets
MAX32665-MAX32668 User Guide Device Resets Four device resets are available – Peripheral Reset, Soft Reset, System Reset, and Power-On Reset. On completion of any of the four reset cycles, all peripherals are reset. On completion of any reset cycle HCLK and PCLK are operational, the CPU core receives clocks and power, and the device is in ACTIVE mode.
Page 61: Peripheral Reset
MAX32665-MAX32668 User Guide Table 4-2: Reset and Low Power Mode Effects Peripheral Soft System ACTIVE SLEEP DEEPSLEEP BACKUP Reset Reset Reset Mode Mode Mode Mode Reset Reset 8kHz Osc 32kHz Osc 7.3728 MHz Osc 60MHz Osc 32MHz Osc 96MHz Osc...
Page 62: System Reset
MAX32665-MAX32668 User Guide To start a Soft Reset, set GCR_RST0.soft_rst = 1. The reset will be completed immediately upon setting GCR_RST0.soft_rst = 1. 4.3.3 System Reset This is the same as Soft Reset except it also resets all GCR, resetting the clocks to their default state. The CPU state is reset as well as the watchdog timers.
Page 63: Instruction Cache Controller
MAX32665-MAX32668 User Guide Figure 4-6: MAX32665—MAX32668 Cache Controllers Control ® ® ® ® Corte x Cortex CPU0 CPU1 SYSTEM BUS INSTRUCTION CACHE INSTRUCTION CACHE SPIXF CACHE SPIXR CACHE INTERNA L INTERNA L CONTROLLER 0 (ICC0) CONTROLLER 1 (ICC1) CONTROLLER (SFCC)
Page 64: Flushing The Icc0/Icc1/Sfcc Cache
MAX32665-MAX32668 User Guide Perform the following steps to enable SFCC. 1. Set PWRSEQ_LPMEMSD.icachexipsd to 0 to ensure the cache power is on. 2. Set SFCC_CACHE_CTRL.enable to 1. 3. Read SFCC_CACHE_CTRL.ready until it returns 1. 4.5.2 Flushing the ICC0/ICC1/SFCC Cache The System Configuration Register (GCR_SCON) includes a field for flushing these caches simultaneously. Setting GCR_SCON.ccache_flush to 1 performs a flush of all three caches.
Page 65: Table 4-6: Iccn Memory Size Register
MAX32665-MAX32668 User Guide Table 4-6: ICCn Memory Size Register ICCn Memory Size ICCn_MEM_SIZE [0x0004] Bits Field Access Reset Description 31:16 memsz Addressable Memory Size Indicates the size of addressable memory by this cache controller instance in 128KB units. 15:0 cchsz Cache Size Returns the size of the cache RAM memory in 1KB units.
Page 66: External Ram Spixr Cache Controller (Srcc)
MAX32665-MAX32668 User Guide SFCC Cache ID SFCC_CACHE_ID [0x0000] Bits Field Access Reset Description relnum Cache Release Number Returns the release number for this Cache instance. Table 4-10: SFCC Memory Size Register SFCC Memory Size SFCC_MEM_SIZE [0x0004] Bits Field Access Reset...
Page 67: Ram Memory Management
MAX32665-MAX32668 User Guide RAM Memory Management This device has many features for managing the on-chip RAM. The on-chip RAM includes data RAM, instruction and data caches, and peripheral FIFOs. 4.8.1 RAM Zeroization The GCR Memory Zeroize Register, GCR_MEM_ZERO, allows clearing memory for firmware or security reasons. Zeroization writes all zeros to the specified memory.
Page 68: Miscellaneous Control Registers
MAX32665-MAX32668 User Guide 4.8.2.1 RAM LIGHTSLEEP RAM can be placed in a low power mode, referred to as LIGHTSLEEP, using the Memory Clock Control Register, GCR_MEM_CLK. LIGHTSLEEP gates off the clock to the RAM and makes the RAM unavailable for read/write operations, while memory contents are retained, reducing power consumption.
Page 69: Table 4-16: Sqwout And Pdown Output Enable Register
MAX32665-MAX32668 User Guide Error Correction Coding Enable MCR_ECCEN [0x0000] Bits Field Access Reset Description Reserved Do not modify this field. sysram5eccen Sysram5 ECC Enable 0: Disable 1: Enable sysram4eccen Sysram4 ECC Enable 0: Disable 1: Enable sysram3eccen Sysram3 ECC Enable...
Page 70: Table 4-18: Control Register
MAX32665-MAX32668 User Guide Comparator Enable MCR_AINCOMP [0x000C] Bits Field Access Reset Description aincomp3pd Comparator 3 Disable 0:Comparator is powered and enabled 1:Comparator is powered down and disabled aincomp2pd Comparator 2 Disable 0:Comparator is powered and enabled 1:Comparator is powered down and disabled...
Page 71: Single Inductor Multiple Output (Simo) Power Supply
MAX32665-MAX32668 User Guide Control MCR_CTRL [0x0010] Bits Field Access Reset Description vddcsw Switch COREB VCOREB can be operated at a lower voltage to minimize leakage in any of the low power modes SLEEP, DEEPSLEEP, and BACKUP. Allows the CPU cores to operate from VCOREA during these low power modes.
Page 72: Single Inductor Multiple Output (Simo) Registers
MAX32665-MAX32668 User Guide Domain Reset REGI Bluetooth transmitter POR TXOUT Bluetooth receiver POR RXOUT USB peripheral reset Power On GPIO pad held in reset until the voltage DDIO rises above threshold. Power On GPIO pad held in reset until the voltage DDIOH rises above threshold.
Page 73: Single Inductor Multiple Output (Simo) Registers Details
MAX32665-MAX32668 User Guide Offset Register Name [0x004C] ZERO_CROSS_CAL_C Reserved Reserved. Do not modify this field. [0x0050] ZERO_CROSS_CAL_D Reserved Reserved. Do not modify this field. 4.13 Single Inductor Multiple Output (SIMO) Registers Details Table 4-21: Buck Voltage Regulator A Control Register...
Page 74: Table 4-23: Buck Voltage Regulator C Control Register
MAX32665-MAX32668 User Guide Table 4-23: Buck Voltage Regulator C Control Register Buck Voltage Regulator A Control VREGO_C [0x000C] Bits Field Access Reset Description 31:8 Reserved Do not modify this field. rangec Regulator Output Range The voltage regulator output range setting.
Page 75: Table 4-26: High Side Fet Peak Current Vrego_C Vrego_D Register
MAX32665-MAX32668 User Guide High Side FET Peak Current VREGO_A VREGO_B IPKA [0x0014] Bits Field Access Reset Description ipksetb 0x8h Reserved Reserved. Do not modify this field. ipkseta 0x8h Reserved Reserved. Do not modify this field. Table 4-26: High Side FET Peak Current VREGO_C VREGO_D Register...
Page 76: Table 4-30: Buck Cycle Count Vrego_C Register
MAX32665-MAX32668 User Guide Table 4-30: Buck Cycle Count VREGO_C Register Buck Cycle Count VREGO_C ILOAD_C [0x0028] Bits Field Access Reset Description 31:8 Reserved Do not modify this field. iloadc Reserved Reserved. Do not modify this field. Table 4-31: Buck Cycle Count VREGO_D Register...
Page 77: Table 4-35: Buck Cycle Count Alert Vrego_D Register
MAX32665-MAX32668 User Guide Table 4-35: Buck Cycle Count Alert VREGO_D Register Buck Cycle Count Alert VREGO_D BUCK_ALERT_THR_D [0x003C] Bits Field Access Reset Description 31:8 Reserved Do not modify this field. buckthrd Reserved Reserved. Do not modify this field. Table 4-36: Buck Regulator Output Ready Register...
Page 78: Power Sequencer And Always-On Domain Registers
MAX32665-MAX32668 User Guide Table 4-38: Zero Cross Calibration VREGO_B Register Zero Cross Calibration VREGO_B ZERO_CROSS_CAL_B [0x0048] Bits Field Access Reset Description 31:5 Reserved Do not modify this field. zxcalb Reserved Reserved. Do not modify this field. Table 4-39: Zero Cross Calibration VREGO_C Register...
Page 79: Power Sequencer And Always-On Domain Register Details
MAX32665-MAX32668 User Guide 4.15 Power Sequencer and Always-On Domain Register Details Table 4-42: Low Power Control Register Low Power Control PWRSEQ_LPCN [0x0000] Bits Field Access Reset Description Reserved Do not modify this field. pdowndslen PDOWN DEEPSLEEP Output Enable 0: Disabled...
Page 80: Table 4-43: Gpio0 Low Power Wakeup Status Flags
MAX32665-MAX32668 User Guide Table 4-43: GPIO0 Low Power Wakeup Status Flags GPIO0 Low Power Wakeup Status Flags PWRSEQ_LPWKST0 [0x0004] Bits Field Access Reset Description 31:0 wakest0 R/W1C GPIO0 Pin Wakeup Status Flag Whenever a GPIO0 pin, in any power mode, transitions from low-to-high or high-to-low, the corresponding bit in this register is set.
Page 81: Table 4-47: Peripheral Low Power Wakeup Status Flags
MAX32665-MAX32668 User Guide 17:0 Wakeen1 GPIO1 Pin Wakeup Interrupt Enable Write 1 to any bit to enable the corresponding pin on the 32-bit GPIO port to generate an interrupt to wakeup the device from any low power mode to ACTIVE mode.
Page 82: Table 4-48: Peripheral Low Power Wakeup Enable Register
MAX32665-MAX32668 User Guide Peripheral Low Power Wakeup Status Flags PWRSEQ_LPPWST [0x0030] Bits Field Access Reset Description aincomp1wkst R/W1C Analog Input Comparator 1 Wakeup Status Flag This bit is set when the comparator inputs detect an event. Write 1 to clear.
Page 83: Table 4-49: Ram Shutdown Control Register
MAX32665-MAX32668 User Guide Peripheral Low Power Wakeup Enable PWRSEQ_LPPWEN [0x0034] Bits Field Access Reset Description usbvbuswken USB VBUS State Change Wakeup Enable Write 1 to enable an interrupt and wakeup the device from any low power mode when PWRSEQ_LPPWST.usbvbuswkst = 1.
Page 84: Table 4-50: Low Power Vdd Power Down Register
MAX32665-MAX32668 User Guide RAM Shutdown Control PWRSEQ_LPMEMSD [0x0040] Bits Field Access Reset Description Reserved Do not modify this field. sram5sd Sysram5 and Sysram11 Shut Down 0: Power enabled. 1: Power shut down. Affected memory is destroyed. Table 4-13 RAM Block Size and Base Address for base address and size information.
Page 85: Global Control Registers (Gcr)
MAX32665-MAX32668 User Guide Low Power VDD Power Down PWRSEQ_LPVDDPD [0x0044] Bits Field Access Reset Description vdd4pd Reserved Reserved. Do not modify this field. vdd3pd Reserved Reserved. Do not modify this field. vdd2pd Reserved Reserved. Do not modify this field. Reserved Reserved.
Page 86: Global Control Register Details (Gcr)
MAX32665-MAX32668 User Guide Offset Register Description [0x0040] GCR_SYS_STAT System Status Flags [0x0044] GCR_RST1 Reset Register 1 [0x0048] GCR_PCLK_DIS1 Peripheral Clocks Disable 1 [0x004C] GCR_EVENT_EN Event Enable Register [0x0050] GCR_REV Revision Register [0x0054] GCR_SYS_STAT_IE System Status Interrupt Enable [0x0064] GCR_ECC_ER Error Correction Coding Error Register...
Page 87: Table 4-55: Reset Register 0
MAX32665-MAX32668 User Guide System Control GCR_SCON [0x0000] Bits Field Access Reset Description dcache_dis SPIXR Cache Controller (SRCC) Disable This disables the SRCC used for SPIXR code and data cache. Setting this field disables the cache and bypasses the cache line buffer.
Page 88 MAX32665-MAX32668 User Guide Reset 0 GCR_RST0 [0x0004] Bits Field Access Reset Description periph_rst Peripheral Reset Write 1 to reset. 0: Not in reset 1: Reset in progress. Note: Watchdog Timers, GPIO Ports, the AoD, RAM Retention and the General Control Registers (GCR) are unaffected.
Page 89 MAX32665-MAX32668 User Guide Reset 0 GCR_RST0 [0x0004] Bits Field Access Reset Description spi2 SPI2 Reset Write 1 to reset. 0: Not in reset 1: Reset in progress. spi1 SPI1 Reset Write 1 to reset. 0: Not in reset 1: Reset in progress.
Page 90: Table 4-56: System Clock Control Register
MAX32665-MAX32668 User Guide Reset 0 GCR_RST0 [0x0004] Bits Field Access Reset Description gpio1 GPIO1 Reset Write 1 to reset. 0: Not in reset 1: Reset in progress. gpio1 GPIO1 Reset Write 1 to reset. 0: Not in reset 1: Reset in progress.
Page 91 MAX32665-MAX32668 User Guide System Clock Control GCR_CLK_CTRL [0x0008] Bits Field Access Reset Description hirc7m_vs 7.3728MHz Internal Oscillator Voltage Source Select In DEEPSLEEP the 7.3728MHz oscillator voltage is sourced by pin V . When exiting DEEPSLEEP the voltage is automatically switched back to this bit setting.
Page 92: Table 4-57: Power Management Register
MAX32665-MAX32668 User Guide System Clock Control GCR_CLK_CTRL [0x0008] Bits Field Access Reset Description 0b001000 Reserved Do not modify this field. Table 4-57: Power Management Register Power Management GCR_PMR 0x000C Bits Field Access Reset Description 31:21 Reserved Do not modify this field.
Page 93: Table 4-58: Peripheral Clock Divisor Register
MAX32665-MAX32668 User Guide Power Management GCR_PMR 0x000C Bits Field Access Reset Description gpiowken GPIO Wakeup Enable Activity on any GPIO pin configured for wakeup causes an exit from SLEEP, DEEPSLEEP, and BACKUP modes. 0: Disabled. 1: Enabled. Reserved Do not modify this field.
Page 94: Table 4-59: Peripheral Clock Disable Register 0
MAX32665-MAX32668 User Guide Table 4-59: Peripheral Clock Disable Register 0 Peripheral Clocks Disable 0 GCR_PCLK_DIS0 [0x0024] Bits Field Access Reset Description spixipm SPIXF Master Clock Disable Disabling a clock disables functionality while also saving power. Reads and writes to peripheral registers are disabled. Peripheral register states are retained.
Page 95 MAX32665-MAX32668 User Guide Peripheral Clocks Disable 0 GCR_PCLK_DIS0 [0x0024] Bits Field Access Reset Description timer2 TMR2 Clock Disable Disabling a clock disables functionality while also saving power. Reads and writes to peripheral registers are disabled. Peripheral register states are retained.
Page 96: Table 4-60: Memory Clock Control Register
MAX32665-MAX32668 User Guide Peripheral Clocks Disable 0 GCR_PCLK_DIS0 [0x0024] Bits Field Access Reset Description spi0 SPI0 Clock Disable Disabling a clock disables functionality while also saving power. Reads and writes to peripheral registers are disabled. Peripheral register states are retained.
Page 97 MAX32665-MAX32668 User Guide Memory Clock Control GCR_MEM_CLK [0x0028] Bits Field Access Reset Description usbls USB FIFO LIGHTSLEEP Enable Data is unavailable for read/write operations in LIGHTSLEEP mode but is retained. 0: ACTIVE mode. 1: LIGHTSLEEP mode enabled. cryptols Crypto RAM LIGHTSLEEP Enable Data is unavailable for read/write operations in LIGHTSLEEP mode but is retained.
Page 98: Table 4-61: Memory Zeroization Control Register
MAX32665-MAX32668 User Guide Memory Clock Control GCR_MEM_CLK [0x0028] Bits Field Access Reset Description sysram3ls Sysram3 LIGHTSLEEP Enable Data is unavailable for read/write operations in LIGHTSLEEP mode but is retained. Table 4-13 RAM for base address and size information. 0: ACTIVE mode.
Page 99 MAX32665-MAX32668 User Guide Memory Zeroization Control GCR_MEM_ZERO [0x002C] Bits Field Access Reset Description usbfifoz USB FIFO Zeroization Write 1 to initiate the operation 0: Operation complete. 1: Operation in progress. cryptoz Crypto MAA Memory Zeroization Write 1 to initiate the operation.
Page 100: Table 4-62: System Status Flag Register
MAX32665-MAX32668 User Guide Memory Zeroization Control GCR_MEM_ZERO [0x002C] Bits Field Access Reset Description sram1z R/W1 Sysram1 Zeroization Write 1 to initiate the operation. 0: Operation complete. 1: Operation in progress. sram0z R/W1 Sysram0 Zeroization Write 1 to initiate the operation.
Page 101 MAX32665-MAX32668 User Guide Reset 1 GCR_RST1 [0x0044] Bits Field Access Reset Description htimer1 HTimer 1 Reset Write 1 to initiate the operation. 0: Operation complete. 1: Operation in progress. htimer0 HTimer 0 Reset Write 1 to initiate the operation. 0: Operation complete.
Page 102: Table 4-64: Peripheral Clock Disable Register 1
MAX32665-MAX32668 User Guide Reset 1 GCR_RST1 [0x0044] Bits Field Access Reset Description owire One-Wire Reset Write 1 to initiate the operation. 0: Operation complete. 1: Operation in progress. sdhc SDHC Reset Write 1 to initiate the operation. 0: Operation complete.
Page 103 MAX32665-MAX32668 User Guide Peripheral Clock Disable 1 GCR_PCLK_DIS1 [0x0048] Bits Field Access Reset Description wdt0 Watchdog Timer 0 Disable Disabling the clock disables functionality while also saving power. Associated register states are retained but read and write access is blocked.
Page 104 MAX32665-MAX32668 User Guide Peripheral Clock Disable 1 GCR_PCLK_DIS1 [0x0048] Bits Field Access Reset Description One-Wire Clock Disable Disabling the clock disables functionality while also saving power. Associated register states are retained but read and write access is blocked. 0: Enabled.
Page 105: Table 4-65: Event Enable Register
MAX32665-MAX32668 User Guide Peripheral Clock Disable 1 GCR_PCLK_DIS1 [0x0048] Bits Field Access Reset Description btle Bluetooth Digital Baseband Clock Disable Disabling the clock disables functionality while also saving power. Associated register states are retained but read and write access is blocked.
Page 106: Table 4-66: Revision Register
MAX32665-MAX32668 User Guide Table 4-66: Revision Register Revision GCR_REV [0x0050] Bits Field Access Reset Description 31:16 Reserved 15:0 revision Device Revision Returns the chip revision ID as a packed BCD. For example, 0xA1 would indicate the device is revision A1.
Page 107: Table 4-69: Error Correction Not Double Error Detected Register
MAX32665-MAX32668 User Guide Error Correction Coding Error GCR_ECC_ER [0x0064] Bits Field Access Reset Description ic1eccerr R/W1C Instruction Cache 1 ECC Error Write to 1 to clear the flag. 0: No error 1: Error ic0eccerr R/W1C Instruction Cache 0 ECC Error Write to 1 to clear the flag.
Page 108 MAX32665-MAX32668 User Guide Error Correction Coding Not Double Error Detected GCR_ECC_NDED [0x0068] Bits Field Access Reset Description fl0eccnded R/W1C Flash0 Not Double ECC Error Detected When cleared, indicates that there is a single correctable error in the Flash0 bank. Write to 1 to clear the flag.
Page 109: Table 4-70: Error Correction Coding Interrupt Enable Register
MAX32665-MAX32668 User Guide Error Correction Coding Not Double Error Detected GCR_ECC_NDED [0x0068] Bits Field Access Reset Description sysram1eccnded R/W1C System RAM1 Not Double ECC Error Detected When cleared, indicates that there is a single correctable error in the RAM1 block. Write to 1 to clear the flag.
Page 110: Table 4-71: Error Correction Coding Address Register
MAX32665-MAX32668 User Guide Table 4-71: Error Correction Coding Address Register Error Correction Coding Address GCR_ECC_ERRAD [0x0070] Bits Field Access Reset Description tagramerr ECC Error Address/TAG RAM Error Data depends on which block has reported the error. If sysram, fl0, or fl1, then this bit(s) represents the bit(s) of the AMBA address of read which produced the error.
Page 111 MAX32665-MAX32668 User Guide Bluetooth LDO Control GCR_BTLE_LDOCR [0x0074] Bits Field Access Reset Description ldotxendly LDOTX Enable Delay Not used. ldotxdisch LDOTX Discharge This bit is used to discharge the LDOTX output using a strong pulldown. For use when switching between Bypass Mode and Regulation Mode.
Page 112: Table 4-73: Bluetooth Ldo Delay Count Register
MAX32665-MAX32668 User Guide Table 4-73: Bluetooth LDO Delay Count Register Bluetooth LDO Delay Count GCR_BTLE_LDODCR [0x0078] Bits Field Access Reset Description 31:29 Reserved 28:20 ldotxdlycnt 0x01B Bluetooth LDOTX Delay Count Not used. 19:17 Reserved 16:8 ldorxdlycnt 0x01B Bluetooth LDORX Delay Count Not used.
Page 113: Function Control Registers
MAX32665-MAX32668 User Guide Arm Peripheral Bus Asynchronous Bridge Select GCR_APB_ASYNC [0x0084] Bits Field Access Reset Description apbasyncI2C0 I2C0 Peripheral Bus Select The access for this peripheral can be performed via one of two different peripheral bus configurations. The system PCLK can be used as any of the other system peripherals that are connected to the APB PCLK domain or a 7.3728MHz...
Page 114: Aes Key Registers
MAX32665-MAX32668 User Guide Function Control 0 GCR_FCR [0x0000] Bits Field Access Reset Description qspi0_fnc_sel QSPI0 Function Select 0: High speed 96MHz oscillator 1: External clock input Note: See the GPIO chapter for the external clock input pin usb_clk_sel USB Reference Clock Source Select This selects the clock source for the USB Hi-Speed Interface.
Page 115: Interrupts And Exceptions
Interrupt Vector Table Table 5-1 lists the interrupt and exception table for the MAX32665—MAX32668. There are 95 interrupt entries for the MAX32665—MAX32668, including reserved for future use interrupt place holders. Including the 15 system exceptions for the Arm Cortex-M4 with FPU, the total number of entries is 110.
Page 116 MAX32665-MAX32668 User Guide Exception Offset Name Description (Interrupt) Number [0x0054] TMR0_IRQHandler Timer 0 Interrupt [0x0058] TMR1_IRQHandler Timer 1 Interrupt [0x005C] TMR2_IRQHandler Timer 2 Interrupt [0x0060] TMR3_IRQHandler Timer 3 Interrupt [0x0064] TMR4_IRQHandler Timer 4 Interrupt [0x0068] TMR5_IRQHandler Timer 5 Interrupt [0x006C]...
Page 117 MAX32665-MAX32668 User Guide Exception Offset Name Description (Interrupt) Number [0x00D0] I2C1_IRQHandler I2C Port 1 Interrupt [0x00D4] Reserved [0x00D8] SPIXC_IRQHandler SPI XIP Interrupt [0x00DC] BTLE_TX_DONE_IRQHandler Bluetooth Transmitter Done Interrupt [0x00E0] BTLE_RX_RCVD_IRQHandler Bluetooth Receive Data Interrupt [0x00E4] BTLE_RX_ENG_DET_IRQHandler Bluetooth Receive Energy Detected...
Page 118 MAX32665-MAX32668 User Guide Exception Offset Name Description (Interrupt) Number [0x0148] SDHC_IRQHandler SDHC Interrupt [0x014C] OWM_IRQHandler 1-Wire Master Interrupt [0x0150] DMA4_IRQHandler DMA4 Interrupt [0x0154] DMA5_IRQHandler DMA5 Interrupt [0x0158] DMA6_IRQHandler DMA6 Interrupt [0x015C] DMA7_IRQHandler DMA7 Interrupt [0x0160] DMA8_IRQHandler DMA8 Interrupt [0x0164] DMA9_IRQHandler...
Page 119: General-Purpose I/O And Alternate Function Pins (Gpio)
Table 6-1 shows the number of GPIO available on each IC package. Some packages and part numbers do not implement all bits of a 32-bit GPIO port. Register fields corresponding to unimplemented GPIO contain indeterminate values and should not be modified. Table 6-1: MAX32665—MAX32668 GPIO Pin Count PACKAGE GPIO...
Page 120: Table 6-2: Max32665-Max32668 Gpio And Alternate Function Matrix, 140 Wlp
MAX32665-MAX32668 User Guide Table 6-2 shows the alternate functions mapped to each GPIO pin. Table 6-2: MAX32665—MAX32668 GPIO and Alternate Function Matrix, 140 WLP GPIO Port[pin] GPIO ALTERNATE ALTERNATE ALTERNATE ALTERNATE FUNCTION 1 FUNCTION 2 FUNCTION 3 FUNCTION 4 GPIO0[0] P0.0...
Page 121: Table 6-3: Max32665-Max32668 Gpio Pin Configuration
Each device pin can be individually configured as a GPIO or an alternate function as shown in Table 6-3. The correct alternate function setting must be selected for each pin of a given multi-pin peripheral for proper operation. Table 6-3: MAX32665—MAX32668 GPIO Pin Configuration MODE GPIOn_EN0 GPIOn_EN1...
Page 122: Table 6-5: Max32665-Max32668 Output Mode Configuration
Output Drive Strength 3, V Supply DDIOH Each GPIO port is assigned a dedicated interrupt vector as shown in the following table. Table 6-6: MAX32665—MAX32668 GPIO Port Interrupt Vector Mapping GPIO Interrupt Status Device Specific Interrupt GPIO Interrupt Source GPIO Interrupt Vector...
Page 123: Usage
MAX32665-MAX32668 User Guide Usage 6.2.1 Reset State During a power-on-reset event, each GPIO is reset to the default input mode with the weak pullup resistor enabled as follows: • The GPIO Configuration Enable bits shown in Table 6-3 are set to I/O (transition to AF1) mode.
Page 124: Gpio Interrupt Handling
A single wakeup interrupt vector, GPIOWAKE_IRQHandler, is assigned for all pins of all GPIO ports. When the GPIO wakeup event occurs, the application software must interrogate each GPIOn_INT_STAT register to determine which external port pin caused the wake-up event. Table 6-7: MAX32665―MAX32668 GPIO Wakeup Interrupt Vector GPIO Wake Interrupt GPIO Wake Interrupt Device Specific Interrupt GPIO Wakeup...
Page 125: Registers
MAX32665-MAX32668 User Guide To enable low power mode wakeup (SLEEP, DEEPSLEEP and BACKUP) using an external GPIO interrupt, complete the following steps: 1. Clear pending interrupt flags by writing to GPIOn_INT_CLR[pin]. 2. Activate the GPIO wakeup function by writing 1 to GPIOn_WAKE_EN[pin].
Page 126: Register Details
31:0 GPIO Configuration Enable, Bit 0 This bit, in conjunction with bits in Table 6-3: MAX32665—MAX32668 GPIO Pin Configuration, configures the corresponding device pin for digital I/O or an alternate function modes. This field can be modified directly by writing to this register or...
Page 127: Table 6-13: Gpio Port N Output Enable Atomic Set Register
MAX32665-MAX32668 User Guide Table 6-13: GPIO Port n Output Enable Atomic Set Register GPIO Port n Output Enable Atomic Set GPIOn_OUT_EN_SET [0x0010] Bits Field Access Reset Description 31:0 GPIO Output Enable Atomic Set Writing 1 to one or more bits sets the corresponding bits in GPIOn_OUT_EN.
Page 128: Table 6-18: Gpio Port N Input Register
MAX32665-MAX32668 User Guide Table 6-18: GPIO Port n Input Register GPIO Port n Input GPIOn_IN [0x0024] Bits Field Access Reset Description 31:0 GPIO Input Returns the state of the input pin only if the corresponding bit in the GPIOn_IN_EN register is set. The state is not affected by the pin’s configuration as an output or alternate function.
Page 129: Table 6-22: Gpio Port N Interrupt Enable Register
MAX32665-MAX32668 User Guide Table 6-22: GPIO Port n Interrupt Enable Register GPIO Port n Interrupt Enable GPIOn_INT_EN [0x0034] Bits Field Access Reset Description 31:0 GPIO Interrupt Enable Enable or disable the interrupt for the corresponding GPIO pin. 0: GPIO interrupt disabled.
Page 130: Table 6-27: Gpio Port N Wakeup Enable Register
MAX32665-MAX32668 User Guide Table 6-27: GPIO Port n Wakeup Enable Register GPIO Port Wakeup Enable GPIOn_WAKE_EN [0x004C] Bits Field Access Reset Description 31:0 GPIO Wakeup Enable Enable the I/O as a wakeup from low power modes (SLEEP, DEEPSLEEP, BACKUP). 0: GPIO is not enabled as a wakeup source from low power modes.
Page 131: Table 6-32: Gpio Port N Pullup Pulldown Selection 1 Register
Description 31:0 GPIO Configuration Enable, Bit 1 This bit, in conjunction with bits in Table 6-3: MAX32665—MAX32668 GPIO Pin Configuration, configures the corresponding device pin as a GPIO or an alternate function mode. Some GPIO are not implemented all devices. The bits associated with unimplemented GPIO should not be changed from their default value.
Page 132: Table 6-36: Gpio Port N Configuration Enable Bit 2 Register
Description 31:0 GPIO Configuration Enable, Bit 2 This bit, in conjunction with bits in Table 6-3: MAX32665—MAX32668 GPIO Pin Configuration, configures the corresponding device pin as a GPIO or an alternate function mode. Some GPIO are not implemented all devices. The bits associated with unimplemented GPIO should not be changed from their default value.
Page 133: Table 6-41: Gpion Pulldown/Pullup Strength Select Register
MAX32665-MAX32668 User Guide Table 6-41: GPIOn Pulldown/Pullup Strength Select Register GPIO Port Pulldown/Pullup Strength Select GPIOn_PS [0x00B8] Bits Field Access Reset Description 31:0 GPIO Pulldown/Pullup Strength Select Selects the strength of the pullup or pulldown resistor for a pin configured for input mode.
Page 134: Flash Controller (Flc)
7-1, below, shows the start address and end address for each flash instance. The internal flash memory is mapped with a start address of 0x1000 0000 and an end address of 0x100F FFFF for a total of 1MB. Table 7-1: MAX32665—MAX32668 Internal Flash Memory Organization Instance...
Page 135: Clock Configuration
MAX32665-MAX32668 User Guide 7.2.1 Clock Configuration The Flash Controller requires a 1MHz peripheral clock for operation. The input clock to the Flash Controller block is the system clock, f . Use the Flash Controller clock divisor to generate f = 1MHz, as shown in Equation 7-1 below.
Page 136: Flash Write
MAX32665-MAX32668 User Guide 7.2.4 Flash Write Writes to a flash location are only successful if the targeted location is already in its erased state. Perform the following steps to write to a flash memory instance: 1. If desired, enable flash controller interrupts by setting the FLCn_INTR.access_error_ie and FLCn_INTR.done_ie bits.
Page 137: Mass Erase
MAX32665-MAX32668 User Guide 7.2.6 Mass Erase CAUTION: Care must be taken to not erase the flash from which application code is currently executing. Mass erase clears the internal flash memory on an instance basis. Perform the following steps to mass erase a single flash memory instance: 1.
Page 138: Flash Controller Register Details
MAX32665-MAX32668 User Guide Flash Controller Register Details Table 7-4: Flash Controller Address Pointer Register Flash Address Register FLCn_ADDR [0x0000] Bits Name Access Reset Description 31:0 addr Flash Address Description This field contains the target address for a write operation. A valid internal flash memory address is required for all write operations.
Page 139: Table 7-7: Flash Controller Interrupt Register
MAX32665-MAX32668 User Guide Flash Controller Control Register FLCn_CTRL [0x0008] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. page_erase R/W1O Page Erase Write a 1 to this field to initiate a page erase at the address in FLCn_ADDR.addr.
Page 140: Table 7-8: Flash Controller Ecc Data Register
MAX32665-MAX32668 User Guide Flash Controller Interrupt Register FLCn_INTR [0x0024] Bits Name Access Reset Description access_fail R/W0C Flash Access Fail Interrupt Flag This bit is set when an attempt is made to write or erase the flash while the flash is busy or locked. Only hardware can set this bit to 1. Writing a 1 to this bit has no effect.
Page 141: Table 7-12: Flash Controller Data Register 3
MAX32665-MAX32668 User Guide Table 7-12: Flash Controller Data Register 3 Flash Controller Data Register 3 FLCn_DATA3 [0x003C] Bits Name Access Reset Description 31:0 data3 Flash Data 3 Flash data for bits 127:96. Maxim Integrated Page 141 of 457...
Page 142: External Memory
MAX32665-MAX32668 User Guide External Memory Overview External memory can be accessed via multiple interfaces. There are three external memory interfaces, two of which are backed by 16KB of cache: • SPI Execute-in-Place FLASH (SPIXF)  16KB dedicated cache • SPI Execute-in-Place RAM (SPIXR) ...
Page 143: Spixf Master Controller
MAX32665-MAX32668 User Guide Figure 8-1. Simplified SPIXF Block Diagram ® ® ® ® Cortex Corte x CPU0 CPU1 SYSTEM BUS SPIXF CACHE CONTROLLER (SFCC) AHB2APB 16KB SYNC ÷ 2 INSTRUCTION CACHE BUS 0 ÷ 2 PCLK SYS_CLK APB 0 MEMORY DECRYPTION...
Page 144: Figure 8-2. Simplified Block Diagram
MAX32665-MAX32668 User Guide data in the Transmit FIFO. At the end of every SPI transfer, data is moved from the shift register into the Receive FIFO. Status flags and interrupts are available to monitor the data levels in these FIFOs.
Page 145: Table 8-1: Spi Header Format
MAX32665-MAX32668 User Guide The format of the header is shown in Table 8-1. If the transaction generates receive data, this data is pushed into the SPI. The Receive FIFO is SPIXFC_FIFO_RX. A complete access sequence to a SPI device is made up of one or more transactions. In some cases, the slave select signal remains asserted across several transactions.
Page 146 MAX32665-MAX32668 User Guide 8.2.1.1.3 Sample SPIXF Master Controller Example Here is an example how to set up the Master Controller: 1. Configure the SPIXF Master Controller mode, number of bytes per page (see SPIXFC_CFG.pgsz and Note below), SCK high and low values, and Slave Select (SS) active timing and inactive timing.
Page 147: Table 8-2: Clock Polarity And Phase Combinations
MAX32665-MAX32668 User Guide Multiple headers and payloads are written to the Transmit FIFO for consecutive execution. As an example, complete the following steps to set up the external SPI flash bus width using the SPIXF Master Controller: 1. Configure the SPIXF Master Controller so it can communicate with the default configuration of the external SPI flash chosen using the appropriate register and header settings.
Page 148 MAX32665-MAX32668 User Guide 8.2.1.1.6 Slave Select Transaction Delay Configuration The transaction delay and slave select timing with respect to the active or inactive slave select edge are determined by a combination of the following register fields: • SPIXFC_CFG.ssact • SPIXFC_CFG.ssiact •...
Page 149: Figure 8-3. Spixfc Transaction Delay
MAX32665-MAX32668 User Guide Figure 8-3. SPIXFC Transaction Delay SPIXFC MODE 0 SPIXFC_CFG.ssact SPIXFC_CFG.hiclk SPIXFC_CFG.ssact SPIXFC_CFG.loclk SPIXFC_CFG.loclk SPIXFC_CFG.inact An extra pulse is provided at the end of this transaction to SPIXFC MODE 3, SPIXFC_SP_CTRL.sckinh3 = 0 comp ly with some SPI f la sh timing d iag ra ms, an d allow f or higher speeds during SPI READ t ransactions.
Page 150: Table 8-3: Encrypted Data Write Order To Spix Flash Memory
MAX32665-MAX32668 User Guide 8.2.1.1.7 Slave Select The SPIXF Master Controller operates with one slave device. A dedicated select pin for slave #0 is provided and controlled by hardware. Both execute-in-place and data storage are supported on slave #0. 8.2.1.1.8 Interrupts Interrupt logic is provided to allow efficient servicing of the SPIXF Master Controller by firmware.
Page 151: Table 8-4. Spixf Master Controller Register Offsets, Names, Access And Description
MAX32665-MAX32668 User Guide 8.2.1.2 SPIXF Master Controller Registers Table 3-1: APB Peripheral Base Address Map for the SPIXF Peripheral Base Offset Address. Table 8-4. SPIXF Master Controller Register Offsets, Names, Access and Description Offset Register Access Description [0x0000] SPIXFC_CFG SPIXF Controller Configuration Register...
Page 152: Table 8-6. Spixf Controller Slave Select Polarity Register
MAX32665-MAX32668 User Guide SPIXF Controller Configuration Register SPIXFC_CFG [0x0000] Bits Name Access Reset Description 15:12 loclk SCK Low Clocks Number of system clocks that SCK is held low when SCK pulses are generated 0: 16 system clocks 1: 1 system clock...
Page 153: Table 8-7. Spixf Controller General Control Register
MAX32665-MAX32668 User Guide Table 8-7. SPIXF Controller General Control Register SPIXF Controller General Control Register SPIXFC_GEN_CTRL [0x0008] Bits Name Access Reset Description 31:26 Reserved for Future Use Do not modify this field. sckfbinv SCK Inversion 0: Use SCK as feedback clock...
Page 154: Table 8-8. Spixf Controller Fifo Control And Status Register
MAX32665-MAX32668 User Guide SPIXF Controller General Control Register SPIXFC_GEN_CTRL [0x0008] Bits Name Access Reset Description sckdr SCK Drive and State This bit reflects the state of the SCK. When in Bit-Bang mode (SPIXFC_GEN_CTRL.bbmode = 1), this bit is written to control the output state of the SCK.
Page 155: Table 8-9. Spixf Controller Special Control Register
MAX32665-MAX32668 User Guide SPIXF Controller FIFO Control and Status Register SPIXFC_FIFO_CTRL [0x000C] Bits Name Access Reset Description 20:16 rfifolvl Receive FIFO Almost Full Level The Almost Full flag is asserted when the number of used FIFO entries (bytes) exceed this value. FIFO depth is 32 bytes.
Page 156: Table 8-10. Spixf Controller Interrupt Status Register
MAX32665-MAX32668 User Guide SPIXF Controller Special Control Register SPIXFC_SP_CTRL [0x0010] Bits Name Access Reset Description Reserved for Future Use Do not modify this field sampl SDIO Sample Mode Enable Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select.
Page 157: Table 8-11. Spixf Controller Interrupt Enable Register
MAX32665-MAX32668 User Guide SPIXF Controller Interrupt Status Register SPIXFC_INT_FL [0x0014] Bits Name Access Reset Description tstall R/W1C Transmit Stalled Interrupt Flag. This flag is set by hardware when the Transmit FIFO is empty, and the selected slave select is asserted.
Page 158: Spixf Master
MAX32665-MAX32668 User Guide 8.2.1.4 SPIXF Master Controller FIFO Registers Table 3-2: AHB Peripheral Base Address Map for the SPIXF Master Controller FIFO Peripheral Base Address. Table 8-12. SPIXF Master Controller FIFO Register Offsets, Names, Access and Description Offset Register Access...
Page 159: Figure 8-4. Supported Spi Configuration
MAX32665-MAX32668 User Guide 8.2.2.1 SPIXF Pin Configuration The SPIXF Master and SPIXF Master Controller use a highly-configurable, flexible, and efficient interface supporting single, dual, or quad I/O. Dedicated pins are provided to support high-speed communication. The following pin configurations are supported and shown in Figure 8-4: •...
Page 160: Figure 8-5. Spixfm Delay Configuration
MAX32665-MAX32668 User Guide causes the slave select to de-assert. The SPIXF block requires reconfiguration prior to subsequent access to external SPI flash space either for execution or data reads. Figure 8-5. SPIXFM Delay Configuration SPIXFM MODE 0 SPIXFM_CFG.ssact SPIXFM_CFG.hiclk SPIXFM_CFG.ssact Several clocks (min 3) SPIXFM_CFG.loclk...
Page 161 MAX32665-MAX32668 User Guide 8.2.2.4 Sample SPIXFM Master Configuration - Execute Code Complete the following steps to execute the SPIXFM Master Configuration sample: 1. Turn on ICache XIP Clock (GCR_PCLK_DIS1.icachexipf = 1). The cache can be put into different power states. See GCR_MEM_CLK for options.
Page 162: Table 8-15. Spixfm Master Register Offsets, Names, Access And Description
MAX32665-MAX32668 User Guide SPIXFM slave select is low, the user must not be executing from SPIXFM space, and the SPIXF block should be reset by setting GCR_RST1.spixip = 1. 8.2.2.7 External SPI Flash Decryption If data in the SPI flash is encrypted when written, it might be transparently decrypted on read back using either code execution or data reads.
Page 163: Table 8-17. Spixfm Fetch Control Register
MAX32665-MAX32668 User Guide SPIXFM Configuration Register SPIXFM_CFG [0x0000] Bits Name Access Reset Description 17:16 ssact Slave Select Active Timing Controls delay from assertion of slave select to start of the SCK pulse and delay from the end of SCK pulses to de-assertion of slave select. See 8.2.1.1.6, above, for details on slave select transaction delay configuration.
Page 164: Table 8-18. Spixfm Mode Control Register
MAX32665-MAX32668 User Guide SPIXFM Fetch Control Register SPIXFM_FETCH_CTRL [0x0004] Bits Name Access Reset Description 15:14 Reserved for Future Use Do not modify this field. 13:12 data_width Data Width Number of data I/O used to receive data. 0b00: Single SDIO 0b01: Dual SDIO...
Page 165: Table 8-19. Spixfm Mode Data Register
MAX32665-MAX32668 User Guide SPIXFM Mode Control Register SPIXFM_MODE_CTRL [0x0008] Bits Name Access Reset Description mdclk Mode Clocks Number of SPI clocks needed during the mode/dummy phase of fetch. Table 8-19. SPIXFM Mode Data Register SPIXFM Mode Data Register SPIXFM_MODE_DATA [0x000C]...
Page 166: Table 8-22. Spixfm Memory Security Control Register
MAX32665-MAX32668 User Guide SPIXFM I/O Control Register SPIXFM_IO_CTRL [0x001C] Bits Name Access Reset Description ss_ds Slave Select Drive Strength This bit controls the drive strength on the dedicated slave select pin. 0: Low Drive Strength. 1: Hi Drive Strength. sck_ds SCK Drive Strength This bit controls the drive strength on the SCK pin.
Page 167: Spi Execute-In-Place Ram (Spixr)
MAX32665-MAX32668 User Guide SPI Execute-in-Place RAM (SPIXR) The SPI Execute-in-Place RAM Master Controller (SPIXR) is an instantiation of the Quad SPI Interface with the following features: • Four SPI modes (mode 0, 1, 2, and 3) • Master mode only support •...
Page 168: Spixr Master Controller Registers
MAX32665-MAX32668 User Guide Figure 8-6. Simplified SPIXR Block Diagram ® ® ® ® Cortex Cortex CPU0 CPU1 AHB SYSTEM B US SPIXR CACHE CONTROLLER (SRCC) 16KB EXTERNAL SPI RAM MEMORY CACHE LINE BUFFER GCR_SCON dcache_dis SPIXR CACHE BYPAS S SPIXR...
Page 169: Spixr Register Details
MAX32665-MAX32668 User Guide Offset Register Access Description [0x0030] SPIXR_STAT SPIXR Active Status Register [0x0034] SPIXR_XMEM_CTRL SPIXR XMEM Control Register 8.3.2 SPIXR Register Details Table 8-25. SPIXR FIFO Data Register SPIXR FIFO Data Register SPIXR_DATA [0x0000] Bits Name Access Reset Description...
Page 170: Table 8-27. Spixr Transmit Packet Size Register
MAX32665-MAX32668 User Guide SPIXR Master Signals Control Register SPIXR_CTRL1 [0x0004] Bits Name Access Reset Description ss_io Master Slave Select Signal Direction This field must be set to 0 for SPIXR operation. 0: Slave Select is an output Note: The SPIXR only operates as a SPI master in single master mode. Writing 1 to this field is invalid.
Page 171: Table 8-29. Spixr Slave Select Timing Register
MAX32665-MAX32668 User Guide SPIXR Static Configuration Register SPIXR_CTRL3 [0x000C] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. 13:12 data_width SPIXR Data Width Sets the number of data lines (SDIO pins) for communication. 0: 1-data pin (Single Mode)
Page 172: Table 8-30. Spixr Master Baud Rate Generator
MAX32665-MAX32668 User Guide SPIXR Slave Select Timing Register SPIXR_SS_TIME [0x0010] Bits Name Access Reset Description 15:8 ssact2 Slave Select Active After Last SCK Number of system clock cycles that SS is active from the last SCK edge to when SS is inactive.
Page 173: Table 8-31. Spixr Dma Control Register
MAX32665-MAX32668 User Guide SPIXR Master Baud Rate Generator Register SPIXR_BRG_CTRL [0x0014] Bits Name Access Reset Description SCK Low Clock Cycles Control Setting this field to 0 disables the low duty cycle control for SCK. Setting this field to any non-zero value sets the high cycle time to: SCK_LOW = lo ×...
Page 174: Table 8-32. Spixr Interrupt Status Flag Register
MAX32665-MAX32668 User Guide SPIXR DMA Control Register SPIXR_DMA [0x001C] Bits Name Access Reset Description tx_fifo_clear Clear the TX FIFO Set this field to 1 to clear the TX FIFO and all TX FIFO related flags in the SPIXR_INT_FL register. When the TX FIFO is cleared, the SPIXR_INT_FL.tx_fifo_empty flag is set by hardware.
Page 175: Table 8-33. Spixr Interrupt Enable Register
MAX32665-MAX32668 User Guide SPIXR Interrupt Status Flag Register SPIXR_INT_FL [0x0020] Bits Name Access Reset Description fault R/W1C Multi-Master Fault Flag Set if the SPI is in Master Mode, Multi-Master Mode is enabled, and a Slave Select input is asserted. A collision also sets this flag.
Page 176: Table 8-34. Spixr Wakeup Flag Register
MAX32665-MAX32668 User Guide SPIXR Interrupt Enable Register SPIXR_INT_EN [0x0024] Bits Name Access Reset Description fault Multi-Master Fault Interrupt Enable 1: Interrupt enabled 0: Interrupt disabled Reserved for Future Use 1: Interrupt enabled 0: Interrupt disabled Slave Select Deasserted Interrupt Enable...
Page 177: Table 8-35. Spixr Wakeup Enable Register
MAX32665-MAX32668 User Guide Table 8-35. SPIXR Wakeup Enable Register SPIXR Wakeup Enable Register SPIXR_WAKE_EN [0x002C] Bits Name Access Reset Description 31:4 Reserved for Future Use Do not modify this field. rx_full Wake on RX FIFO Full Enable Set to 1 to wake up the device when this RX FIFO is full.
Page 178: Spixr Cache Controller (Srcc)
SPI-XiP RAM device. The SRCC includes tag RAM, cache RAM and a line fill buffer as shown in Figure 4-6: MAX32665—MAX32668 Cache Controllers Control. Write allocate and critical word first are options controlled by the application. Each cache line is 256-bits wide with the lower 5-bits of the address used as the cache line index.
Page 179: Srcc Registers
MAX32665-MAX32668 User Guide 8.4.4 SRCC Registers Table 3-1: APB Peripheral Base Address Map for the SRCC Peripheral Base Address. Table 8-38: External Memory Cache Controller Register Addresses and Descriptions Offset Register Name Access Description [0x0000] SRCC_CACHE_ID Cache ID Register [0x0004]...
Page 180: Table 8-42: Srcc Invalidate Register
MAX32665-MAX32668 User Guide SRCC Cache Control Register SRCC_CACHE_CTRL [0x0100] Bits Name Access Reset Description 15:3 Reserved for Future Use Do not modify this field. cwfst_dis Critical Word First (CWF) Disable Setting this field to 1 disables Critical Word First operation. When CWF is disabled, the cache fills the cache line before sending the data to the Arm Cortex core.
Page 181: Secure Digital Host Controller
Details of the SD communication and protocol are not part of the scope of this document. The MAX32665—MAX32668 SDHC only supports a single SD card. SD memory card and SDIO card specifications are available at https://www.sdcard.org.
Page 182: Instances
8.5.1 Instances The SDHC pin mapping for the SD Host Controller Standard Specification Version 3.0 are shown in Table 8-43, below. Table 8-43: MAX32665—MAX32668 SDHC Alternate Function Mapping to SDHC Specification Pin Names SDHC Alternate Function Specification Alternate Function Number...
Page 183: Sdhc Peripheral Clock Selection
MAX32665-MAX32668 User Guide SDHC Alternate Function Specification Alternate Function Number Pin Name Pin Name Direction Signal Description SDHC_DAT3 P1.0 DAT[3] SD data bus bit 3. For configuration of the GPIO for SDHC peripheral usage see the General-Purpose I/O and Alternate Function Pins chapter.
Page 184: Sd Command Generation
MAX32665-MAX32668 User Guide Figure 8-9: SD Bus Protocol - Multi-Block Read Operation Figure 8-10: SD Bus Protocol - Multi Block Write Operation 8.5.4 SD Command Generation Table 8-44 shows the registers required for three transaction types: SDMA generated transactions, ADMA generated transactions, and CPU transactions (includes data transfers and Non-DAT transfers).
Page 185: Sdhc Registers
MAX32665-MAX32668 User Guide Register SDMA Command ADMA Command CPU Data Transfer Non-DAT (No Data) Transfer Argument 2 No (Protected) SDHC_SDMA Command SDHC_CMD 8.5.5 SDHC Registers Table 3-1: APB Peripheral Base Address Map for the SDHC Peripheral Base Address Table 8-45: SDHC Register Offsets, Names and Descriptions...
Page 186: Sdhc Register Details
MAX32665-MAX32668 User Guide Offset Register Name Description [0x0050] SDHC_FORCE_CMD Force Event Register for Auto CMD Error Status [0x0052] SDHC_FORCE_EVENT_INT_STAT Force Event Register for Error Interrupt Status [0x0054] SDHC_ADMA_ER ADMA Error Status register [0x0058] SDHC_ADMA_ADDR_0 ADMA System Address register 0 [0x005C]...
Page 187: Table 8-47: Sdhc Sdma Block Size Register
MAX32665-MAX32668 User Guide Table 8-47: SDHC SDMA Block Size Register SDMA Block Size Register SDHC_BLK_SIZE [0x0004] Bits Name Access Reset Description 31:15 Reserved for Future Use Do not modify this field. 14:12 host_buf Host SDMA Buffer Size This field specifies the size of the contiguous buffer in the system memory for SDMA transfers.
Page 188: Table 8-48: Sdhc Sdma Block Count Register
MAX32665-MAX32668 User Guide Table 8-48: SDHC SDMA Block Count Register SDMA Block Count Register SDHC_BLK_CNT [0x0006] Bits Name Access Reset Description 31:16 Reserved for Future Use Do not modify this field. 15:0 trans 0x0200 Current Transfer Block Count Set to the total number of blocks to transfer prior to a block transfer operation. Set the Block Count Enable (SDHC_TRANS.blk_cnt_en) bit to 1 for a block transfer.
Page 189 MAX32665-MAX32668 User Guide SDMA Transfer Mode Register SDHC_TRANS [0x000C] Bits Name Access Reset Description read_write Data Transfer Direction Select Sets the direction for DAT line data transfers. Set to 1 to transfer data from the SD card to the SDHC (Read). For all other commands, set this bit to 0 (Write).
Page 190: Table 8-51: Summary Of How Register Settings Determine Type Of Data Transfer
MAX32665-MAX32668 User Guide Table 8-51: Summary of how register settings determine type of data transfer Multi/Single Block Select Block Count Enable Block Count Function SDHC_TRANS.multi SDHC_TRANS.blk_cnt_en SDHC_BLK_CNT.trans N.A. N.A. Single transfer N.A. Infinite transfer ≠0 Multiple transfer Stop Multiple transfer...
Page 191: Table 8-53: Relationship Between Parameters And The Name Of Response Type
Table 8-62 shows the mapping from the Response Registers to the SD Host Controller Standard Specification REP[127:0] notation for the MAX32665—MAX32668. Table 8-63 shows the SD types of response mapped to the MAX32665—MAX32668 Response registers. Maxim Integrated Page 191 of 457...
Page 192: Table 8-57: Sdhc Response 3 Register
MAX32665-MAX32668 User Guide Table 8-57: SDHC Response 3 Register Response 3 Register SDHC_RESP_3 [0x0016] Bits Name Access Reset Description 15:0 cmd_resp Response Register 3 Response 7 to Response 0 registers are referenced as a contiguous, single register in the SD Host Controller Spec V3.0.
Page 193: Table 8-61: Sdhc Response 7 Register
MAX32665-MAX32668 User Guide Table 8-61: SDHC Response 7 Register Response 7 Register SDHC_RESP_7 [0x001E] Bits Name Access Reset Description 15:0 cmd_resp Response Register 7 Response 7 to Response 0 registers are referenced as a contiguous, single register in the SD Host Controller Spec V3.0.
Page 194 MAX32665-MAX32668 User Guide Present State Register SDHC_PRESENT [0x0024] Bits Name Access Reset Description 23:20 dat_signal_level SDHC_DAT[3:0] Line Signal Level Indicates the DAT line level for error recovery and debugging. Use to detect the busy signal level as indicated on SDHC_DAT[0].
Page 195 MAX32665-MAX32668 User Guide Present State Register SDHC_PRESENT [0x0024] Bits Name Access Reset Description read_transfer Read Transfer Active Indicates completion of a read transfer. This bit is set to 1 for either of the following conditions: 1) After the end bit of a Read command.
Page 196: Table 8-66: Sdhc Host Control 1 Register
1. 1: Card Inserted 0: No card inserted ext_data_transfer_width Extended Data Transfer Width Extended data transfer width is not supported on the MAX32665—MAX32668. Always reads 0. 0: Bus width is selected by SHDC_HOST_CN_1.data_transfer_width field dma_select DMA Select Sets the DMA mode.
Page 197: Table 8-67: Sdhc Power Control Register
MAX32665-MAX32668 User Guide Host Control 1 Register SDHC_HOST_CN_1 [0x0028] Bits Name Access Reset Description led_cn LED Control 1: LED on 0: LED off Table 8-67: SDHC Power Control Register Power Control Register SDHC_PWR [0x0029] Bits Name Access Reset Description Reserved for Future Use Do not modify this field.
Page 198 MAX32665-MAX32668 User Guide Block Gap Control Register SDHC_BLK_GAP [0x002A] Bits Name Access Reset Description read_wait Read Wait Control If the card supports read wait (optional for SDIO cards), setting this bit enables use of the read wait protocol to stop reading data using the SDHC_DAT[2] line. If the card does not support read wait, the SDHC stops the SD Clock to hold read data, preventing command generation.
Page 199: Table 8-69: Sdhc Wakeup Control Register
MAX32665-MAX32668 User Guide Table 8-69: SDHC Wakeup Control Register Wakeup Control Register SDHC_WAKEUP [0x002B] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. card_rem Wakeup Event Enable on SD Card Removal Enable wakeup event interrupt when the SDHC_INT_STAT.card_removal flag occurs.
Page 200 MAX32665-MAX32668 User Guide Clock Control Register SDHC_CLK_CN [0x002C] Bits Name Access Reset Description upper_sdclk_freq_sel Upper Bits of SDCLK Frequency Select Bits 9 and 8 of the 10-bit SDCLK frequency select. See the SDHC_CLK_CN.sdclk_freq_sel field for details about the clock select calculation.
Page 201: Table 8-71: Sdhc Timeout Control Register
MAX32665-MAX32668 User Guide Table 8-71: SDHC Timeout Control Register Timeout Control Register SDHC_TO [0x002E] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. data_count_value Data Timeout Counter Value Determines the interval for DAT line timeout detection. The timeout clock frequency is generated by dividing PCLK by the value calculated using this register.
Page 202: Table 8-72: Sdhc Software Reset Register
MAX32665-MAX32668 User Guide Table 8-72: SDHC Software Reset Register Software Reset Register SDHC_SW_RESET [0x002F] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. reset_dat RWAC Software Reset for DAT Line 1: Reset 0: Ready The following registers and fields are cleared/initialized when this bit is set:...
Page 203: Table 8-73: Sdhc Normal Interrupt Status Register
MAX32665-MAX32668 User Guide 8.5.6.1 Normal Interrupt Status Register The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt Signal Enable does not. An interrupt is generated when the Normal Interrupt Signal Enable is enabled, and at least one of the status bits is set to 1. Writing 1 to a bit of the RW1C attribute clears it.
Page 204 MAX32665-MAX32668 User Guide Normal Interrupt Status Register SDHC_INT_STAT [0x0030] Bits Name Access Reset Description buff_rd_ready RW1C Buffer Read Ready Set if the Buffer Read Enable field in the Present State register (SDHC_PRESENT.buff_rd_ready) changes from 0 to 1. 1: Ready to read buffer...
Page 205: Table 8-74: Transfer Complete And Data Timeout Error Priority And Status
MAX32665-MAX32668 User Guide Table 8-74: Transfer Complete and Data Timeout Error Priority and Status Transfer Complete Data Timeout Error Status SDHC_INT_STAT.trans_comp SDHC_ER_INT_STAT.data_to Interrupted by another event Timeout occurred during transfer Command execution complete Table 8-75: Command Complete and Command Timeout Error Priority and Status...
Page 206 CMD12, but also when Auto CMD12 is not executed due to a previous command error. current_limit R/W1C Current Limit Error Not supported on MAX32665—MAX32668 data_end_bit R/W1C Data End Bit Error Set if a 0 is detected at the end bit position of read data that uses the DAT line or the end-bit position of the CRC status.
Page 207: Table 8-77: Sdhc Normal Interrupt Status Register
MAX32665-MAX32668 User Guide Error Interrupt Status Register SDHC_ER_INT_STAT [0x0032] Bits Name Access Reset Description cmd_crc R/W1C Command CRC Error Set for the following cases: 1) If a response is returned, and the Command Timeout Error is set to 0, then this error flag is set if a CRT error is detected in the Command Response.
Page 208: Table 8-78: Sdhc Error Interrupt Status Enable Register
MAX32665-MAX32668 User Guide Normal Interrupt Status Enable Register SDHC_INT_EN [0x0034] Bits Name Access Reset Description buffer_rd Buffer Read Ready Status Enable Set to enable Buffer Read Ready status. 1: Enabled 0: Disabled buffer_wr Buffer Write Ready Status Enable Set to enable Buffer Write Ready status.
Page 209: Table 8-79: Sdhc Normal Interrupt Signal Enable Register
MAX32665-MAX32668 User Guide Error Interrupt Status Enable Register SDHC_ER_INT_EN [0x0036] Bits Name Access Reset Description auto_cmd_12 Auto CMD12 Error Status Interrupt Enable 1: Enabled 0: Disabled Reserved for Future Use Do not modify this field. data_end_bit Data End Bit Error Status Interrupt Enable...
Page 210: Table 8-80: Sdhc Error Interrupt Signal Enable Register
MAX32665-MAX32668 User Guide Normal Interrupt Signal Enable Register SDHC_INT_SIGNAL [0x0038] Bits Name Access Reset Description card_insert Card Insertion Signal Enable 1: Enabled 0: Disabled buffer_rd Buffer Read Ready Signal Enable 1: Enabled 0: Disabled buffer_wr Buffer Write Ready Signal Enable...
Page 211: Table 8-81: Sdhc Auto Cmd Error Status Register
MAX32665-MAX32668 User Guide Error Interrupt Signal Enable Register SDHC_ER_INT_SIGNAL [0x003A] Bits Name Access Reset Description data_end_bit Data End Bit Error Signal Enable 1: Enabled 0: Disabled data_crc Data CRC Error Signal Enable 1: Enabled 0: Disabled data_to Data Timeout Error Signal Enable...
Page 212: Table 8-82: Sdhc Host Control 2 Register
1: The Host Controller hardware sets the above fields using the Preset Value register settings. asynch_int Asynchronous Interrupt Enable Always reads 0. Asynchronous Interrupt Enable is not supported by the MAX32665—MAX32668. Writes to this field have no effect. 13:8 Reserved for Future Use Do not modify this field. Maxim Integrated...
Page 213: Table 8-83: Sdhc Capabilities Register 0
MAX32665-MAX32668 User Guide Host Control 2 Register SDHC_HOST_CN_2 [0x003E] Bits Name Access Reset Description sampling_clk Sampling Clock Select This field is automatically set by hardware when Execute Tuning (SDHC_HOST_CN_2. execute) is cleared. 0: The fixed clock is used to sample data 1: The tuned clock is used to sample data Note: The Card Driver cannot write 1 to this bit.
Page 214 MAX32665-MAX32668 User Guide Capabilities Register 0 SDHC_CFG_0 [0x0040] Bits Name Access Reset Description Reserved for Future Use 1_8v Voltage Support 1.8V 1: 1.8V supported 3_0v Voltage Support 3.0V 1: 3.0V supported 3_3v Voltage Support 3.3V 1: 3.3V supported suspend Suspend/Resume Support...
Page 215: Table 8-84: Sdhc Capabilities Register 1
MAX32665-MAX32668 User Guide Table 8-84: SDHC Capabilities Register 1 Capabilities Register 1 SDHC_CFG_1 [0x0044] Bits Name Access Reset Description 31:24 Reserved for Future Use Do not modify this field. 23:16 clk_multi Clock Multiplier Always reads 0x00. 0: Programmable clock generation is not supported.
Page 216: Table 8-85: Sdhc Maximum Current Capabilities Register
MAX32665-MAX32668 User Guide Table 8-85: SDHC Maximum Current Capabilities Register Maximum Current Capabilities Register SDHC_MAX_CURR_CFG [0x0048] Bits Name Access Reset Description 31:24 Reserved for Future Use Do not modify this field. 23:16 1_8v Maximum Current for 1.8V 0x00: System dependent...
Page 217: Table 8-88: Sdhc Adma Error Status Register
MAX32665-MAX32668 User Guide Force Event Register for Error Interrupt Status SDHC_FORCE_EVENT_INT_STAT [0x0052] Bits Name Access Reset Description 11:10 Reserved for Future Use Do not modify this field. adma Force Event for ADMA Error 1: Interrupt is generated 0: No interrupt generated...
Page 218: Table 8-89: Sdhc Adma System Address Register 0
MAX32665-MAX32668 User Guide ADMA Error Status Register SDHC_ADMA_ER [0x0054] Bits Name Access Reset Description len_mismatch ADMA Length Mismatch Error This error occurs in the following two cases: 1) When setting Block Count Enable, the total data length specified by the Descriptor Table is different from that specified by the Block Count and Block Length fields.
Page 219: Table 8-90: Sdhc Adma System Address Register 1
MAX32665-MAX32668 User Guide Table 8-90: SDHC ADMA System Address Register 1 ADMA System Address Register 1 SDHC_ADMA_ADDR_1 [0x005C] Bits Name Access Reset Description 31:0 addr ADMA System Address 1 Most-significant word for the 64-bit ADMA address. See SDHC_ADMA_ADDR_0 details. 8.5.6.4...
Page 220: Table 8-93: Sdhc Preset Value 0 To Preset Value 7 Registers
Interrupt Signals Indicates the logical OR of Interrupt Signal and Wakeup Signal for the single slot. Only one slot is defined for the MAX32665—MAX32668, slot 0. Reset by POR and by software reset for all (SDHC_SW_RESET.reset_all). Maxim Integrated Page 220 of 457...
Page 221: Table 8-95: Sdhc Host Controller Version Register
MAX32665-MAX32668 User Guide Table 8-95: SDHC Host Controller Version Register Host Controller Version Register SDHC_HOST_CN_VER [0x00FE] Bits Name Access Reset Description 15:8 vend_ver Vendor Version This status is reserved for the vendor version number. The Host Driver should not use this status.
Page 222: Standard Dma (Dmac)
MAX32665-MAX32668 User Guide Standard DMA (DMAC) The Standard Direct Memory Access controller (DMAC) is a hardware feature that provides the ability to perform high- speed, block memory transfers of data independent of an Arm core. All DMAC transactions consist of burst read from the source into the internal DMA FIFO followed by an burst write from the internal DMA FIFO to the destination.
Page 223: Dma Channel Operation (Dmach)
MAX32665-MAX32668 User Guide Table 9-1: MAX32665—MAX32668 DMAC and Channel Instances DMACm Instance DMACHn Channel Instance DMACH0 DMACH1 DMACH2 DMACH3 DMAC0 DMACH4 DMACH5 DMACH6 DMACH7 DMACH0 DMACH1 DMACH2 DMACH3 DMAC1 DMACH4 DMACH5 DMACH6 DMACH7 DMA Channel Operation (DMACH) 9.2.1 DMA Channel Arbitration and DMA Bursts DMAC contains an internal arbiter that allows enabled channels to access the AHB and move data.
Page 224: Dma Source And Destination Addressing
The DMACHn_CFG.srcinc field is ignored when the DMA source is a peripheral memory, and the DMACHn_CFG.dstinc field is ignored when the DMA destination is a peripheral memory. Table 9-2: MAX32665—MAX32668 DMAC Source and Destination by Peripheral DMACHn_CFG.reqs Peripheral...
Page 225 MAX32665-MAX32668 User Guide DMACHn_CFG.reqs Peripheral DMA Source DMA Destination 0x1C Reserved 0x1D Reserved 0x1E Reserved 0x1F Reserved 0x20 Reserved 0x21 SPI0 DMACHn_SRC SPI0 Transmit FIFO 0x22 SPI1 DMACHn_SRC SPI1 Transmit FIFO 0x23 Reserved 0x24 UART0 DMACHn_SRC UART0 Transmit FIFO 0x25...
Page 226: Data Movement From Source To Dma
MAX32665-MAX32668 User Guide DMACHn_CFG.reqs Peripheral DMA Source DMA Destination 0x3F Reserved Data Movement From Source to DMA Table 9-3 shows the fields that control the burst movement of data into the DMA FIFO. The source is a peripheral or memory.
Page 227: Usage
MAX32665-MAX32668 User Guide Usage Use the following procedure to perform a DMA transfer from a peripheral’s receive FIFO to memory, from memory to a peripheral’s transmit FIFO, or from memory to memory. 1. Ensure DMACHn_CFG.chen, DMACHn_CFG.rlden = 0, and DMACHn_ST.ctz_st = 0.
Page 228: Chaining Buffers
MAX32665-MAX32668 User Guide At this point, there are two possible responses depending on the value of the DMACHn_CFG.rlden: 1. If DMACHn_CFG.rlden = 1, then the DMACHn_SRC, DMACHn_DST, and DMACHn_CNT registers are loaded from the reload registers, and the channel remains active and continues operating using the newly-loaded address/count values and the previously programmed configuration values.
Page 229: Figure 9-1: Dma Block-Chaining Flowchart
MAX32665-MAX32668 User Guide Figure 9-1: DMA Block-Chaining Flowchart DMA TRANSFER RESET DMA rlden = 0 chen = 0 ctz_st = 1 CONFIGURE DMA TRANSFER PARAMETERS Set brst, dstinc, dstwd, srcinc, and srcwd CONFIGURE DMA DMACHn_CNT TRANSFER PARAMETERS CLEAR CTZ FLAG...
Page 230: Dma Interrupts
MAX32665-MAX32668 User Guide DMA Interrupts Enable interrupts for each channel by setting DMACn_CN.chien. When an interrupt for a channel is pending, the corresponding DMACn_INT.ipend = 1. Set the corresponding enable bit to cause an interrupt when the flag is set.
Page 231: Memory-To-Memory Dma
MAX32665-MAX32668 User Guide The start of the timeout period is controlled by DMACHn_CFG.reqwait: • If DMACHn_CFG.reqwait = 0, the timer begins counting immediately after DMACHn_CFG.to_sel is configured to a value other than 0x0. • If DMACHn_CFG.reqwait = 1, the timer begins counting when the first DMA request is received from the peripheral.
Page 232: Dma Channel Registers
MAX32665-MAX32668 User Guide Table 9-8: DMACn Interrupt Register DMACn Interrupt DMACn_INT [0x0004] Bits Field Access Reset Description 31:0 ipend DMACHn Channel Interrupt Flag Each bit in this field represents an interrupt for the corresponding channel interrupt m. To clear an interrupt, clear the corresponding active interrupt bit in the DMACHn_ST register.
Page 233: Dma Channel Register Details
MAX32665-MAX32668 User Guide 9.13 DMA Channel Register Details Table 9-11: DMACHn Configuration Register DMA Channel n Configuration DMACHn_CFG [0x0100] Bits Field Access Reset Description ctzien CTZ Interrupt Enable 0: Disabled 1: Enabled. DMACn_INT.ipend is set to 1 whenever a CTZ event occurs.
Page 234: Table 9-12: Dma Status Register
Request Select Selects the source and destination for the transfer as shown in Table 9-2: MAX32665—MAX32668 DMAC Source and Destination by Peripheral. Channel Priority Sets the priority of the channel relative to other channels of DMAm. Channels of the same priority are serviced in a round-robin fashion.
Page 235: Table 9-13: Dmachn Source Register
MAX32665-MAX32668 User Guide DMA Channel n Status DMACHn_ST [0x0104] Bits Field Access Reset Description to_st R/W1C Timeout Status Timeout status field. Write 1 to clear. 0: No time out. 1: A channel time out has occurred Reserved bus_err R/W1C Bus Error If this bit reads 1, an AHB abort occurred and the channel was disabled by hardware.
Page 236: Table 9-14: Dma Channel N Destination Register
MAX32665-MAX32668 User Guide Table 9-14: DMA Channel n Destination Register DMA Channel n Destination DMACHn_DST [0x010C] Bits Field Access Reset Description 31:0 Destination Device Address For peripheral transfers, the actual address field is either ignored or forced to zero because peripherals only have one location to read/write data based on the request select chosen.
Page 237: Table 9-18: Dma Channel N Count Reload Register
MAX32665-MAX32668 User Guide Table 9-18: DMA Channel n Count Reload Register DMA Count Reload DMAn_CNT_RLD [0x011C] Bits Field Access Reset Description rlden Reload Enable. Enables automatic loading of the DMACHn_SRC, DMACHn_DST, and DMACHn_CNT registers when a CTZ event occurs. Set this bit after the address reload registers are programmed.
Page 238: Cyclic Redundancy Check Engine (Crc)
MAX32665-MAX32668 User Guide 10. Cyclic Redundancy Check Engine (CRC) The Cyclic Redundancy Checks (CRCs) engine can perform CRC functions on data stored in SRAM. The CRC engine cannot be used to perform a CRC of data stored in flash memory.
Page 239: Instances
MAX32665-MAX32668 User Guide When found in literature, sometimes the LSB or MSB of the polynomial is omitted when the polynomial is written in binary. It is more common to see CRC polynomials with the MSB implied because that is the bit that is shifted off, XOR’d with the ��...
Page 240: Registers
MAX32665-MAX32668 User Guide Figure 10-1: Galois Field CRC and LFSR Architecture Different polynomials generate different sequences of random data. Ideally, an n-bit polynomial generates a random �� sequence of 2 − 1 bits. Not all polynomials are maximal length. Some repeat before the theoretical maximum length of ��...
Page 241: Register Details
MAX32665-MAX32668 User Guide Offset Register Name Access Description [0x0034] CRC_DATA_OUT1 CRC Data Output Register 0 (Bits 63:32) [0x0038] CRC_DATA_OUT2 CRC Data Output Register 0 (Bits 95:64) [0x003C] CRC_DATA_OUT3 CRC Data Output Register 0 (Bits 127:96) [0x0040] CRC_POLY CRC Polynomial Register...
Page 242 MAX32665-MAX32668 User Guide Crypto Control Register CRYPTO_CTRL [0x0000] Bits Name Access Reset Description 13:12 Reserved for Future Use Do not modify this field. 11:10 rdsrc Read FIFO Source Select This field selects the source of the read FIFO. The default is for the Read FIFO to not use DMA as its source buffer.
Page 243: Table 10-3: Crc Control Register
MAX32665-MAX32668 User Guide Table 10-3: CRC Control Register CRC Control Register CRC_CTRL [0x000C] Bits Name Access Reset Description 31:2 Reserved for Future Use Do not modify this field. MSB Select Set the order of calculating the CRC on the input data.
Page 244: Table 10-7: Crc Data Input Registers
MAX32665-MAX32668 User Guide Table 10-7: CRC Data Input Registers CRC Data Input Register 0 CRC_DATA_IN0 [0x0020] CRC Data Input Register 1 CRC_DATA_IN1 [0x0024] CRC Data Input Register 2 CRC_DATA_IN2 [0x0028] CRC Data Input Register 3 CRC_DATA_IN3 [0x002C] Bits Name Access...
Page 245: Table 10-10: Crc Value Register
MAX32665-MAX32668 User Guide Table 10-10: CRC Value Register CRC Value Register CRC_VAL [0x0044] Bits Name Access Reset Description 31:0 CRC Value This is the state for the Galois Field. Output of the CRC calculation or the current state of the LFSR.
Page 246: Analog To Digital Converter And Comparators (Adc)
The external analog input signals are defined as alternate functions on GPIO as shown in Table 6-2: MAX32665—MAX32668 GPIO and Alternate Function Matrix, 140 WLP. The 10-bit ADC conversions are stored as a 16- bit value selectable as most-significant bit (MSB) or least-significant bit (LSB) aligned. The 8 external analog inputs can be configured as 4 two-input comparators with interrupt capabilities.
Page 247: Architecture
MAX32665-MAX32668 User Guide 11.3 Architecture The ADC is a first-order sigma-delta converter with a 10-bit output. The ADC operates at a maximum frequency of 8MHz with a fixed-sample rate as shown in Equation 11-1. Details of selecting the ADC clock frequency, f...
Page 248: Figure 11-1: Analog To Digital Converter Block Diagram
MAX32665-MAX32668 User Guide Figure 11-1: Analog to Digital Converter Block Diagram PWRSEQ_LPPWEN GCR_PMR COMPARATOR_IRQ aincompnwken compwken ADC_CTRL ADC_CTRL ref_sel ref_scale ADC_CTRL COMPARATORS INTERNA L adc_pwr REFERENCE ADC CONTROL 1.22V (ADC_CTRL) MCR_AINCOMP aincompnpd REFERENCE ENABLE ADC LIMIT 0 (ADC_LIMIT0) ENABLE LIMIT CONTROL...
Page 249: Clock Configuration
MAX32665-MAX32668 User Guide 11.4 Clock Configuration The ADC clock, adcclk, is controlled by the GCR_PCLK_DIV.adcfrq register field. Configure this field for the target ADC sample frequency. The maximum clock supported by the ADC is 8MHz. The divisor selection, GCR_PCLK_DIV.adcfrq, for the ADC depends on the peripheral clock.
Page 250: Power-Up Sequence
MAX32665-MAX32668 User Guide 11.5 Power-Up Sequence Complete the following steps to configure the ADC: 1. Disable the ADC clock by setting ADC_CTRL.clk_en to 0. 2. Set the ADC clock (adcclk) using GCR_PCLK_DIV.adcfrq. See Clock Configuration 3. Enable the ADC clock by setting ADC_CTRL.clk_en to 1 4.
Page 251: Ain0 - Ain7 Scale Limitations
MAX32665-MAX32668 User Guide 11.7.1 AIN0 – AIN7 Scale Limitations The external inputs, AIN0 through AIN7, support scaling of the input by 50%, the reference by 50%, or both by 50%. Also, the scaling can further be modified by additional factors of 2, 3, or 4 as defined by ADC_CTRL.adc_divsel. The scale settings...
Page 252: Data Conversion Value Equations
MAX32665-MAX32668 User Guide Table 11-4: ADC Data Register Alignment Options ADC_CTRL.data_align = 0 15 14 13 12 11 10 ADC_DATA data ADC_CTRL.data_align = 1 15 14 13 12 11 10 ADC_DATA data 11.7.4 Data Conversion Value Equations Use the following equations to calculate the ADC data value for a conversion for the selected channel. If using the internal reference, V = 1.22V;...
Page 253: Data Limits And Out Of Range Interrupts
MAX32665-MAX32668 User Guide 11.7.5 Data Limits and Out of Range Interrupts Channel limits are implemented to minimize power consumption for power supply monitoring. The ADC includes four limit registers, ADC_LIMIT0 to ADC_LIMIT3, that you can use to set a high limit, low limit, and the ADC channel number to apply the limits against.
Page 254: Power-Down Sequence
MAX32665-MAX32668 User Guide Complete the following steps to enable a high and low limit for an ADC input channel using the ADC_LIMIT0 register. Perform these steps after the ADC is configured for measurement, and the configuration is identical for all four limit registers except for the limit register name: 1.
Page 255: Registers
MAX32665-MAX32668 User Guide 11.9 Registers Table 3-1: APB Peripheral Base Address Map for the base peripheral address of these registers. All fields are reset on peripheral, system, or power-on reset events unless otherwise specified. Table 11-5. ADC Registers Summary Offset...
Page 256 MAX32665-MAX32668 User Guide ADC Control ADC_CTRL [0x0000] Bits Field Access Reset Description 16:12 adc_ch_sel ADC Channel Select Selects the active channel for the next ADC conversion. ADC Input adc_ch_sel Input Channel 0x00 AIN0 0x01 AIN1 0x02 AIN2 0x03 AIN3 0x04...
Page 257: Table 11-7: Adc Status Register
MAX32665-MAX32668 User Guide ADC Control ADC_CTRL [0x0000] Bits Field Access Reset Description start Start ADC Conversion Write this bit to 1 to start an ADC conversion. When the conversion is complete, the hardware automatically sets this bit to 0 indicating the conversion is complete.
Page 258: Table 11-10: Adc Limit 0 To 3 Registers
MAX32665-MAX32668 User Guide ADC Interrupt Control ADC_INTR [0x000C] Bits Field Access Reset Description adc_hi_limit_if R/W1C ADC High Limit Interrupt Flag 1: The last conversion resulted in a high-limit condition for one of the limit registers. ref_ready_if R/W1C ADC Reference Ready Interrupt Flag 0: Not Ready 1: Ready.
Page 259 MAX32665-MAX32668 User Guide ADC Limit 0 ADC_LIMIT0 [0x0010] ADC Limit 1 ADC_LIMIT1 [0x0014] ADC Limit 2 ADC_LIMIT2 [0x0018] ADC Limit 3 ADC_LIMIT3 [0x001C] Bits Field Access Reset Description 23:22 Reserved for Future Use Do not modify this field. 21:12 ch_hi_limit 0x3FF High Limit Threshold Sets the threshold for high-limit comparisons.
Page 260: Uart
MAX32665-MAX32668 User Guide 12. UART The industry-standard UART ports communicate with external devices using standard serial communications protocols. The UARTs are full-duplex Universal Asynchronous Receiver/Transmitter (UART) serial ports. Each UART instance supports identical functionality and registers unless specifically noted otherwise.
Page 261: Uart Interrupts
MAX32665-MAX32668 User Guide (UARTn_CTRL0.parity_en=1). Parity can be based on the number of logic high bits or logic low bits in the receive characters as set in the register bit UARTn_CTRL0.parity_lvl. Break frames are transmitted by setting the field UARTn_CTRL0.break to 1. A break sets all bits in the frame to 0.
Page 262: Table 12-2: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps
MAX32665-MAX32668 User Guide Equation 12-1: UART Bit Rate Divisor Equation UART_BIT_RATE_CLK DIV = where, (7−UARTn_BAUD0.��) ×Target Baud Rate) Target Baud Rate is the desired UART interface speed is the UART interface time base frequency. This frequency is either f or the 7.3728MHz clock.
Page 263: Uart Configuration And Operation
MAX32665-MAX32668 User Guide target bit rate because it is the smallest value that results in DIV ≥ 1. Using 3 for UARTn_BAUD0.clkdiv, UARTn_BAUD0.ibaud is 1, which is the integer portion of the 1.63 DIV calculation. The UARTn_BAUD1.dbaud field calculation based on UARTn_BAUD0.clkdiv = 3, UARTn_BAUD0.ibaud = 1 and DIV = 1.63 is: UARTn_BAUD1.
Page 264: Register Details
MAX32665-MAX32668 User Guide Table 12-3: UART Register Summary Offset Name Description [0x0000] UARTn_CTRL0 UARTn Control 0 Register [0x0004] UARTn_CTRL1 UARTn Control 1 Register [0x0008] UARTn_STAT UARTn Status Register [0x000C] UARTn_INT_EN UARTn Interrupt Enable Register [0x0010] UARTn_INT_FL UARTn Interrupt Flag Register...
Page 265 MAX32665-MAX32668 User Guide UART Control 0 UARTn_CTRL0 [0x0000] Bits Field Access Reset Description stop Stop Bit Mode Select Select the number of stop bits per character. The default is 1 stop bit, stop = 0. Setting this field to 1 enables 1.5 stop bits for a 5-bit character size and 2 stop bits for all other character sizes.
Page 266: Table 12-5: Uart Control 1 Register
MAX32665-MAX32668 User Guide UART Control 0 UARTn_CTRL0 [0x0000] Bits Field Access Reset Description parity_en Parity Enable If parity is enabled, parity is generated and verified based on the UARTn_CTRL0.parity_mode field. 0: No parity checking or generation. 1: Parity generation and checking is enabled.
Page 267: Table 12-7: Uart Interrupt Enable Register
MAX32665-MAX32668 User Guide UART Status UARTn_STAT [0x0008] Bits Field Access Reset Description 13:8 rx_num Number of characters in the Receive FIFO Read this field to determine the number of characters in the receive FIFO. tx_full Transmit FIFO Full Status 0: FIFO is not full.
Page 268: Table 12-8: Uart Interrupt Flags Register
MAX32665-MAX32668 User Guide UART Interrupt Enable UARTn_INT_EN [0x000C] Bits Field Access Reset Description tx_fifo_lvl Transmit FIFO Threshold Level Interrupt Enable Enables the Transmit FIFO threshold level interrupt. This interrupt occurs when the number of entries in the Transmit FIFO is equal or less than the value set in UARTn_CTRL1.tx_fifo_lvl.
Page 269 MAX32665-MAX32668 User Guide UART Interrupt Flags UARTn_INT_FL [0x0010] Bits Field Access Reset Description break R/W1C Received Break Interrupt Flag When the UART receives a series of BREAK frames, this flag is set when the first BREAK frame is received. Write 1 to clear this field.
Page 270: Table 12-9: Uart Rate Integer Register
MAX32665-MAX32668 User Guide Table 12-9: UART Rate Integer Register UART Baud Rate Integer UARTn_BAUD0 [0x0014] Bits Field Access Reset Description 31:19 Reserved for Future Use Do not modify this field. 18:16 clkdiv Bit Rate Clock Divisor This field is used to divide the bit rate clock by the selected Clock Divider value.
Page 271: Table 12-13: Uart Transmit Fifo Data Output Register
MAX32665-MAX32668 User Guide UART DMA Configuration Register UARTn_DMA [0x0020] Bits Field Access Reset Description 21:16 rxdma_lvl Receive FIFO Level DMA Trigger If the Receive FIFO level is greater than this value, the DMA channel transfers data from the Receive FIFO. DMA transfers continue until the Receive FIFO is empty.
Page 272: I C Master/Slave Serial Communications Peripheral (I2C)
C slave at standard data rates. For simplicity, I2Cn is used throughout this section to refer to any of the I2C peripherals. The MAX32665—MAX32668 has the ability to access the I2Cn peripherals via two different busses (clock sources). Bus 0 is the traditional I...
Page 273: Figure 13-1: I C Block Diagram
MAX32665-MAX32668 User Guide Figure 13-1: I C Block Diagram ® ® ® ® Corte x Corte x CPU0 CPU1 SYSTEM BUS (AHB) AHB2APB AHB2APB BASE ADDRE SSES BUS 0 BUS 1 SYNC ÷ 2 ASYNC ÷ 1 I2Cn BUS 0 BUS 1 ÷...
Page 274: C Master/Slave Features
Diagram. Table 13-1: MAX32665 – MAX32668 I2C Peripheral Pins lists the locations of the SDA and SCL signals for each of the I2Cn peripherals per package. Table 13-1: MAX32665 – MAX32668 I C Peripheral Pins I2Cn ALTERNATE FUNCTION ALT FUNCTION #...
Page 275: I 2 C Overview
MAX32665-MAX32668 User Guide 13.3 C Overview 13.3.1 I C Bus Terminology Table 13-2, below, contains terms and definitions used in this chapter for the I C Bus Terminology. Table 13-2: I C Bus Terminology Term Definition Transmitter The device that sends data to the bus.
Page 276: Bit Transfer Process
MAX32665-MAX32668 User Guide condition to abort the transfer, or it can generate a repeated START condition (that is, send a START condition without an intervening STOP condition) to start a new transfer. A receiver can generate a NACK after a byte transfer if any of the following conditions occur: •...
Page 277: I 2 C Configuration And Usage
I2Cn_CLK_LO registers for the desired I C operating frequency. The MAX32665—MAX32668 has the ability to select the source for the I C peripheral clock. Application code can select between the system peripheral clock, f (accessed via I2Cn Bus 0 registers), or the 7.3728MHz oscillator (accessed via PCLK I2Cn Bus 1 registers).
Page 278: Scl Clock Generation For Hs-Mode
MAX32665-MAX32668 User Guide Figure 13-3: I C SCL Timing for Standard, Fast, and Fast-Plus Modes I2Cn_CLK_HI.scl_hi I2Cn_CLK_LO.scl_lo I2Cn_CLK_HI.scl_hi IH_MIN IL_MAX During synchronization, external masters or external slaves may be driving SCL simultaneously. This affects the SCL duty cycle. By monitoring SCL, the controller can determine whether an external master or slave is holding SCL low. In either case, the controller waits until SCL is high before starting to count the number of SCL high cycles.
Page 279: I 2 C Addressing
MAX32665-MAX32668 User Guide Equation 13-4: I C Peripheral Source Clock Period , GCR_APB_ASYNC. apbasyncI2Cn = 0 SYS_CLK I2C_CLK 7.3728MHz, GCR_APB_ASYNC. apbasyncI2Cn = 1 In Hs-mode, the analog glitch filter within the device adds a minimum delay of t = 10ns.
Page 280: I 2 C Master Mode Operation
MAX32665-MAX32668 User Guide In 7-bit addressing mode, the master sends one address byte. To address a 7-bit address slave, first clear I2Cn_MSTR_MODE.sea= 0, then write the address to the TX FIFO formatted as follows where An is address A6:A0. Master Writing to Slave : 7-bit address : [A6 A5 A4 A3 A2 A1 A0 0] Master Reading from Slave : 7-bit address : [A6 A5 A4 A3 A2 A1 A0 1] In 10-bit addressing mode (I2Cn_MSTR_MODE.sea = 1), the first byte the master sends is the 10-bit Slave Addressing byte...
Page 281 MAX32665-MAX32668 User Guide For master mode operation, the following registers should only be configured when either 1) the I C peripheral disabled, or 2) the I C bus is guaranteed to be idle/free. If this peripheral is the only master on the bus, then changing the registers outside of a transaction (I2Cn_MSTR_MODE.start = 0) will satisfy this requirement:...
Page 282 MAX32665-MAX32668 User Guide 13.4.6.2 C Master Mode Transmitter Operation When in Master Mode, initiating a Master Transmitter operation begins with the following sequence: 1. Write the I C Slave Address Byte to the I2Cn_FIFO register with the R/W bit set to 0 2.
Page 283: I 2 C Slave Mode Operation
MAX32665-MAX32668 User Guide Also, in a multi-master environment, application firmware does not need to wait for the bus to become free before attempting to start a transaction (writing 1 to I2Cn_MSTR_MODE.start). If the bus is free when I2Cn_MSTR_MODE.start is set to 1, the transaction begins immediately. If instead the bus is busy, then the peripheral will: 1.
Page 284 MAX32665-MAX32668 User Guide For slave mode operation, the following registers should be configured with the I2C peripheral disabled: • I2Cn_CTRL0.mst – 0 for Slave operation. • I2Cn_CTRL0.gcen • I2Cn_CTRL0.irxm – The recommended value for this field is 0. Also, note that a setting of 1 is incompatible with slave mode operation with clock stretching disabled (I2Cn_CTRL0.scl_strd=1).
Page 285 MAX32665-MAX32668 User Guide Program flow for transmit operation in just-in-time mode is as follows: 1. With I2Cn_CTRL0.i2cen = 0, initialize all relevant registers, including specifically for this mode I2Cn_CTRL0.scl_strd = 0, I2Cn_TX_CTRL0[5:2] = 0x8 and I2Cn_TX_CTRL0.txpreld=0. Don't forget to program I2Cn_CLK_HI.scl_hi and I2Cn_HS_CLK.hs_clk_hi with appropriate values satisfying tSU;DAT (and HS tSU;DAT).
Page 286 MAX32665-MAX32668 User Guide To use slave transmit preload mode: 1. With I2Cn_CTRL0.i2cen = 0, initialize all relevant registers, including specifically for this mode I2Cn_CTRL0.scl_strd = 1, I2Cn_TX_CTRL0[5:2] = 0xF and I2Cn_TX_CTRL0.txpreld=1. 2. SW sets I2Cn_CTRL0.i2cen = 1. Even though the controller is enabled, at this point it will not ACK an address match with R/W=1 until SW sets I2Cn_TX_CTRL1.txrdy =1.
Page 287 MAX32665-MAX32668 User Guide If the TX FIFO is not ready (I2Cn_TX_CTRL1.txrdy = 0) and the I C controller receives a data read request from the master, the hardware automatically sends a NACK at the end of the first address byte. The setting of the Do Not Respond field is...
Page 288: I 2 C Interrupt Sources
MAX32665-MAX32668 User Guide 13.4.8 I C Interrupt Sources The I C controller has a very flexible interrupt generator that generates an interrupt signal to the Interrupt Controller on any of several events. On recognizing the I C interrupt, firmware determines the cause of the interrupt by reading the I...
Page 289: Tx Fifo Preloading
MAX32665-MAX32668 User Guide During a receive transaction (which during master operation is a READ, and during slave operation is a WRITE), received bytes are automatically written to the RX FIFO. Software should monitor the RX FIFO level and unload data from it as needed by reading I2Cn_FIFO.
Page 290: Interactive Receive Mode (Irxm)
MAX32665-MAX32668 User Guide When TX FIFO Preloading is enabled, the software controls ACKs to the external master using the TX Ready (I2Cn_TX_CTRL1.txrdy) bit. When I2Cn_TX_CTRL1.txrdy is set to 0, hardware automatically NACKs all read transactions from the Master. Setting I2Cn_TX_CTRL1.txrdy to 1 sends an ACK to the Master on the next read transaction and transmits the data in the TX FIFO.
Page 291: Clock Stretching
MAX32665-MAX32668 User Guide Note: Interactive Receive Mode does not apply to general call address responses or START byte responses. Note: When enabling Interactive Receive Mode and operating as a slave, clock stretching must remain enabled (I2Cn_CTRL0.scl_strd = 0). 13.4.12 Clock Stretching...
Page 292: I 2 C Dma Control
MAX32665-MAX32668 User Guide The timeout feature is disabled when I2Cn_TIMEOUT.to = 0 and is enabled for any non-zero value. When the timeout is enabled, the timeout timer starts counting when the I C peripheral hardware drives SCL low and is reset by the I peripheral hardware when the SCL line is released.
Page 293: Register Details
MAX32665-MAX32668 User Guide Offset Name Description [0x0004] I2Cn_STAT C Status Register [0x0008] I2Cn_INT_FL0 C Interrupt Flags 0 Register [0x000C] I2Cn_INT_EN0 C Interrupt Enable 0 Register [0x0010] I2Cn_INT_FL1 C Interrupt Flags 1 Register [0x0014] I2Cn_INT_EN1 C Interrupt Enable 1 Register [0x0018]...
Page 294: Table 13-7: I C Status Register
MAX32665-MAX32668 User Guide I2C Control 0 I2Cn_CTRL0 [0x0000] Bits Field Access Reset Description SDA Status 0: SDA pin is logic low. 1: SDA pin is logic high. SCL Status 0: SCL pin is logic low. 1: SCL pin is logic high.
Page 295: Table 13-8: I C Interrupt Flag 0 Register
MAX32665-MAX32668 User Guide I2C Status I2Cn_STAT [0x0004] Bits Field Access Reset Description ckmd Master Mode I C Bus Transaction Active The peripheral is operating in Master mode and a valid transaction beginning with a START command is in progress on the I C bus.
Page 296 MAX32665-MAX32668 User Guide I2C Interrupt Flag 0 I2Cn_INT_FL0 [0x0008] Bits Field Access Reset Description stoperi R/W1C Out of Sequence STOP Interrupt Flag This flag is set if a STOP condition occurs out of expected sequence. Write 1 to clear this field. Writing 0 has no effect.
Page 297: Table 13-9: I C Interrupt Enable 0 Register
MAX32665-MAX32668 User Guide I2C Interrupt Flag 0 I2Cn_INT_FL0 [0x0008] Bits Field Access Reset Description txthi TX FIFO Threshold Level Interrupt Flag This field is set by hardware if the number of bytes in the Transmit FIFO is less than or equal to the Transmit FIFO threshold level. Write 1 to clear. This field is automatically cleared by hardware when the TX FIFO contains fewer bytes than the TX threshold level.
Page 298 MAX32665-MAX32668 User Guide I2C Interrupt Enable 0 I2Cn_INT_EN0 [0x000C] Bits Field Access Reset Description stoperie Out of Sequence STOP Condition Detected Interrupt Enable 0: Disabled. 1: Enabled. strterie Out of Sequence START Condition Detected Interrupt Enable 0: Disabled. 1: Enabled.
Page 299: Table 13-10: I C Interrupt Flag 1 Register
MAX32665-MAX32668 User Guide Table 13-10: I C Interrupt Flag 1 Register I2C Interrupt Status Flags 1 I2Cn_INT_FL1 [0x0010] Bits Field Access Reset Description 31:3 Reserved starti R/W1C START Condition Status Flag If set, a device START condition has been detected.
Page 300: Table 13-14: I C Receive Control 1 Register
MAX32665-MAX32668 User Guide I2C Receive Control 0 I2Cn_RX_CTRL0 [0x001C] Bits Field Access Reset Description 11:8 rxth RX FIFO Threshold Level Set this field to the required number of bytes to trigger a RX FIFO threshold event. When the number of bytes in the RX FIFO is equal to or greater than this field, the hardware sets the I2Cn_INT_FL0.rxthi bit indicating an RX FIFO...
Page 301: Table 13-15: I C Transmit Control 0 Register
MAX32665-MAX32668 User Guide Table 13-15: I C Transmit Control 0 Register I2C Transmit Control 0 I2Cn_TX_CTRL0 [0x0024] Bits Field Access Reset Description 31:12 Reserved 11:8 txth TX FIFO Threshold Level Sets the level for a Transmit FIFO threshold event interrupt. If the number of bytes remaining in the TX FIFO falls to this level or lower the interrupt flag I2Cn_INT_FL0.txthi is set indicating a TX FIFO Threshold Event occurred.
Page 302: Table 13-16: I C Transmit Control 1 Register
MAX32665-MAX32668 User Guide I2C Transmit Control 0 I2Cn_TX_CTRL0 [0x0024] Bits Field Access Reset Description gcamtxafdis TX FIFO General Call Address Match Auto Flush Disable Various situations or conditions are described in this user guide that lead to the Transmit FIFO being flushed and locked out (I2Cn_INT_FL0.txloi = 1).
Page 303: Table 13-18: I C Master Mode Control Register
MAX32665-MAX32668 User Guide I2C Data I2Cn_FIFO [0x002C] Bits Field Access Reset Description data 0xFF C FIFO Data Register Reads from this register pops data off the RX FIFO. Writes to this register pushes data onto the TX FIFO. Reading from an empty RX FIFO returns 0xFF. Writes to a full TX FIFO are ignored.
Page 304: Table 13-21: I C Hs-Mode Clock Control Register
MAX32665-MAX32668 User Guide C Clock High Control I2Cn_CLK_HI [0x0038] Bits Field Access Reset Description scl_hi 0x001 Clock High Time In Master Mode, this configures the SCL high time. = 1 f × ( scl_hi + 1 ) ⁄ SCL_HI I2C_CLK...
Page 305: Table 13-24: I C Slave Address Register
MAX32665-MAX32668 User Guide I2C DMA I2Cn_DMA [0x0048] Bits Field Access Reset Description rxen RX DMA Channel Enable 0: Disable 1: Enable txen TX DMA Channel Enable 0: Disable 1: Enable Table 13-24: I C Slave Address Register C Slave Address...
Page 306: Quad Serial Peripheral Interface (Spi)
• Multi-master mode fault detection Figure 14-1: QSPI Block Diagram shows the structure of the peripheral. See Table 14-1: MAX32665—MAX32668 SPI Instances for the peripheral-specific peripheral bus assignment and bit rate generator clock source. Maxim Integrated Page 306 of 457...
Page 307: Instances
Instances The following instances of the peripheral are provided. For a specific instance replace n in register names with either 0, 1, or 2 depending on the instance of the peripheral. Table 14-1: MAX32665—MAX32668 SPI Instances Formats Bit Rate Generator...
Page 308: Spi Formats
Other slave select signals into the peripheral are ignored in slave mode. The MAX32665—MAX32668 supports up to three slave select lines for each instance, QSPIn_SS0, QSPIn_SS1 and QSPIn_SS2. In a typical SPI network, the master device selects the slave device using the slave select output. The master starts the communication by selecting the slave device by asserting the slave select output.
Page 309: Three-Wire Spi
MAX32665-MAX32668 User Guide Figure 14-2: 4-Wire SPI Connection Diagram 14.2.2 Three-Wire SPI The signals in three-wire SPI operation are shown in Table 14-4: Three-Wire Format Signals, The MOSI signal is used as a bi- directional, half-duplex I/O referred to as Slave Input Slave Output (SISO). Three-wire SPI also uses a serial clock signal generated by the master and a slave select pin controlled by the master.
Page 310: Pin Configuration
MAX32665-MAX32668 User Guide Figure 14-3: Generic 3-Wire SPI Master to Slave Connection 14.3 Pin Configuration Before configuring the QSPIn peripheral, first disable any SPI activity for the port by setting the QSPIn_CTRL0.enable field to 14.3.1 QSPIn Alternate Function Mapping Pin selection and configuration is required to use the QSPIn port. The following information applies to SPI master and slave operation as well as three-wire, four-wire, dual and quad mode communications.
Page 311: Dual Mode Format Configuration
MAX32665-MAX32668 User Guide 14.3.4 Dual Mode Format Configuration In Dual mode SPI two I/O pins are used to transmit 2-bits of data per SCK clock cycle. The communication is half-duplex and the direction of the data transmission must be known by both the master and slave for a given transaction. Dual mode SPI...
Page 312: Spi Peripheral Clock
MAX32665-MAX32668 User Guide 14.4.2 SPI Peripheral Clock The System Peripheral Clock, PCLK, drives the QSPIn peripheral clock. The SPI0 provides an internal clock, SPI0_CLK, that is used within the SPI peripheral for the base clock to control the module and generate the SCK clock when in master mode.
Page 313: Qspin Fifos
MAX32665-MAX32668 User Guide Figure 14-6: SPI Clock Polarity For proper data transmission, the clock phase and polarity must be identical for the SPI master and slave. The master always places data on the MOSI line a half-cycle before the SCK edge for the slave to latch the data.
Page 314: Registers
MAX32665-MAX32668 User Guide The following FIFO interrupts are supported: • Transmit FIFO Empty • Transmit FIFO Threshold • Receive FIFO Full • Receive FIFO threshold • Transmit FIFO Underrun  Slave mode only, master mode stalls the serial clock •...
Page 315: Register Details
MAX32665-MAX32668 User Guide 14.6 Register Details Table 14-7: QSPIn FIFO Data Register QSPIn FIFO Data Register QSPIn_DATA [0x0000] Bits Name Access Reset Description 31:0 qspififo QSPIn FIFO Data Register This register is used for the QSPI Transmit and Receive FIFO. Reading from this register returns characters from the Receive FIFO and writing to this register adds characters to the Transmit FIFO.
Page 316: Table 14-9: Qspin Transmit Packet Size Register
MAX32665-MAX32668 User Guide QSPIn Control 0 Register QSPIn_CTRL0 [0x0004] Bits Name Access Reset Description ss_io Master Slave Select Signal Direction Set the I/O direction for 0: Slave Select is an output 1: Slave Select is an input Note: This field is only used when the QSPIn is configured for Master Mode (QSPIn_CTRL0.mm_en = 1).
Page 317 MAX32665-MAX32668 User Guide QSPIn Control 2 Register QSPIn_CTRL2 [0x000C] Bits Name Access Reset Description three_wire Three-Wire SPI Enable Set this field to 1 to enable three-wire SPI communication. Set this field to 0 for four-wire full-duplex SPI communication. 0: Four-wire full-duplex mode enabled.
Page 318: Table 14-11: Qspin Slave Select Timing Register
MAX32665-MAX32668 User Guide QSPIn Control 2 Register QSPIn_CTRL2 [0x000C] Bits Name Access Reset Description clkpol Clock Polarity This field controls the SCK polarity. The default clock polarity is for SPI Mode 0 and Mode 1 operation and is active high. Invert the SCK polarity for SPI Mode 2 and Mode 3 operation.
Page 319: Table 14-12: Qspin Master Clock Configuration Registers
MAX32665-MAX32668 User Guide Table 14-12: QSPIn Master Clock Configuration Registers QSPIn Master Clock Configuration Register QSPIn_CLK_CFG [0x0014] Bits Name Access Reset Description 31:20 Reserved for Future Use Do not modify this field. 19:16 scale SPI Peripheral Clock Scale Scales the QSPI input clock (PCLK for QSPI0/QSPI1 and HCLK for QSPI2) by 2scale to generate the QSPIn peripheral clock.
Page 320: Table 14-14: Qspin Interrupt Status Flags Registers
MAX32665-MAX32668 User Guide QSPIn DMA Control Register QSPIn_DMA [0x001C] Bits Name Access Reset Description 20:16 rx_fifo_level 0x00 RX FIFO Threshold Level Set this value to the desired RX FIFO threshold level. When the RX FIFO contains the number of bytes or greater than this field, a DMA request is triggered, and QSPIn_INT_FL.rx_thresh is set.
Page 321: Table 14-15: Qspin Interrupt Enable Registers
MAX32665-MAX32668 User Guide QSPIn Interrupt Status Flags Register QSPIn_INT_FL [0x0020] Bits Name Access Reset Description m_done R/W1C Master Data Transmission Done Flag Set if SPI is in Master Mode, and all transactions have completed. Reserved for Future Use Do not modify this field.
Page 322: Table 14-16: Qspin Wakeup Status Flags Registers
MAX32665-MAX32668 User Guide QSPIn Interrupt Enable Register QSPIn_INT_EN [0x0024] Bits Name Access Reset Description abort Slave Mode Abort Detected Interrupt Enable 0: Interrupt is disabled 1: Interrupt is enabled fault Multi-Master Fault Interrupt Enable 0: Interrupt is disabled 1: Interrupt is enabled Reserved for Future Use Do not modify this field.
Page 323: Table 14-17: Qspin Wakeup Enable Registers
MAX32665-MAX32668 User Guide Table 14-17: QSPIn Wakeup Enable Registers QSPIn Wakeup Enable Register QSPIn_WAKE_EN [0x002C] Bits Name Access Reset Description 31:4 Reserved for Future Use Do not modify this field. rx_full Wake on RX FIFO Full Enable 0: Wake event is disabled 1: Wake event is enabled.
Page 324: Htimer (Ht)
MAX32665-MAX32668 User Guide 15. HTimer (HT) 15.1 Overview The HTimer (HT) is a 40-bit binary timer similar to the real-time clock but is driven by a high-speed internal clock source. The timer provides a short-interval, auto-reload alarm and a long-interval alarm. Configurable alarm settings allow it to be used as a low-power wakeup timer.
Page 325: Register Access Control
MAX32665-MAX32668 User Guide 15.3 Register Access Control The hardware provides a collision-protection mechanism that prevents software from reading registers at the same time they are being updated by hardware, and vice versa. 15.3.1 Register Write Protection The HTIMER_CTRL.busy bit is a read-only status bit controlled by hardware and set when any of the following conditions occur: •...
Page 326: Registers
MAX32665-MAX32668 User Guide 15.4 Registers Table 3-1: APB Peripheral Base Address Map for the HTimer Register Peripheral Base Addresses. All fields are reset on peripheral, system, or power-on reset events unless otherwise specified. Table 15-1. HTimer Registers Summary Offset Register...
Page 327: Table 15-6: Htimer Control Register
MAX32665-MAX32668 User Guide Table 15-6: HTimer Control Register HTimer Control HTIMER_CTRL [0x0010] Bits Field Access Reset Description 31:16 Reserved for Future Use Do not modify this field from its default value. write_en Write Enable Software must set this bit to 1 before writing to HTIMER_CTRL.enable.
Page 328 MAX32665-MAX32668 User Guide HTimer Control HTIMER_CTRL [0x0010] Bits Field Access Reset Description enable HT Enable Enables and disables the timer. Software must write HTIMER_CTRL.write_en = 1 before changing this field. HTIMER_CTRL.busy must read 0 before writing to this bit. After writing to this bit, check the HTIMER_CTRL.busy flag for 0 to determine when the HT synchronization is complete.
Page 329: Timers
Gated: Timer increments only when timer input pin is asserted. • Capture/Compare: Timer counts when timer input is asserted, captures timer count when input is deasserted. The MAX32665–MAX32668 provide six instances of the timer peripheral (TMR0, TMR1, TMR2, TMR3, TMR3, TMR5). 16.1 Features •...
Page 330: Timer Pin Functionality
MAX32665-MAX32668 User Guide 16.3 Timer Pin Functionality Most timers have an associated timer pin that can function as an optional input or output depending on the selected timer mode. The timer pin functionality is mapped as an alternate function that is shared with a GPIO. Timer pin assignments are detailed in the data sheet for the specific device.
Page 331: One-Shot Mode Timer Period
MAX32665-MAX32668 User Guide 16.4.1 One-Shot Mode Timer Period The timer period ends on the timer clock following TMRn_CNT = TMRn_CMP. The timer peripheral automatically performs the following actions at the end of the timer period: TMRn_CNT is reset to 0x0000 0001.
Page 332: Continuous Mode Timer Period
MAX32665-MAX32668 User Guide Figure 16-2: Continuous Mode Diagram TIMER CLOCK TMR_CN.TEN TMR_CMP TMR_CNT 0X0000_0002 0X0000_0001* 0X0000_0000** TMR_INT.IRQ SOFTW ARE CLEARS BIT SOFTW ARE CLEARS BIT TMR_CN.TPL = 0 TIMER PIN (OUTPUT) TMR_CN.TPL = 1 * TMR_CNT AUTOMATICALLY RELOADS WITH 0X0000_0001 AT THE END OF THE TIMER PERIOD, BUT SOFTW ARE CAN WRITE ANY I NITIAL VALUE TO TMR_CNT BEFORE THE TIMER IS ENABLE D.
Page 333: Continuous Mode Configuration
MAX32665-MAX32668 User Guide The timer peripheral automatically performs the following actions at the end of the timer period: TMRn_CNT is reset to 0x0000 0001. The timer remains enabled and continues incrementing. 2. If the timer output is enabled, the timer pin toggles state (low to high or high to low).
Page 334: Counter Mode (010B)
MAX32665-MAX32668 User Guide 16.6 Counter Mode (010b) In Counter mode, the timer peripheral increments TMRn_CNT when a transition occurs on the timer pin. When TMRn_CNT = TMRn_CMP, the interrupt bit is set and the TMRn_CNT register is set to 0x0000 0001 and continues incrementing.
Page 335: Counter Mode Timer Period
MAX32665-MAX32668 User Guide 16.6.1 Counter Mode Timer Period The timer period ends on the rising edge of PCLK following TMRn_CNT = TMRn_CMP. The timer peripheral automatically performs the following actions at the end of the timer period: TMRn_CNT is reset to 0x0000 0001. The timer remains enabled and continues incrementing on selected transitions of the timer pin.
Page 336: Pwm Mode (011B)
MAX32665-MAX32668 User Guide 16.7 PWM Mode (011b) In PWM mode, the timer sends a Pulse-Width Modulated (PWM) output using the timer’s output signal. The timer first counts up to the match value stored in the TMRn_PWM register. At the end of the cycle where the...
Page 337 MAX32665-MAX32668 User Guide If TMRn_CN.tpol is 0, the ratio of the PWM output high time to the total period is calculated using Equation 16-7, below. Equation 16-7: Timer PWM Output High Time Ratio with Polarity 0 ( TMR_CMP – TMR_PWM ) PWM output high time ratio ( % ) = ×...
Page 338: Capture Mode (100B)
MAX32665-MAX32668 User Guide 16.8 Capture Mode (100b) Capture mode most often used to measure the time between events. The timer increments from an initial value until an edge transition occurs on the timer pin. This triggers the ‘capture’ event which copies TMRn_CNT to the TMRn_PWM.pwm...
Page 339: Capture Mode Timer Period
MAX32665-MAX32668 User Guide 16.8.1 Capture Mode Timer Period Two timer period events are possible in Capture Mode: The Capture event occurs on the timer clock following the selected transition on the timer pin. The timer peripheral automatically performs the following actions: 1.
Page 340: Compare Mode Timer Period
MAX32665-MAX32668 User Guide Figure 16-5: Counter Mode Diagram TIMER CL OCK CNT_CL K TMR_CN.ten 0xFFFF FFFF TMR_CMP.cmp TMR_CNT 0x0000 0002 0x00 00 0 001* 0x0000 0000** TMR_INT.irq FIRMWARE CLEARS TMR_INT.irq BIT TMR_CN.tpol = 0 TIMER OUTPUT TMR_CN.tpol = 1 * TMR_CNT AUTOMATICALLY RELOADS WITH 0x0000 0001 AT THE END OF THE TI MER PERI OD. FIRMWARE SETS THE INITIAL VALUE FOR TMR_CNT BEFORE THE TIMER IS ENABLE D.
Page 341: Compare Mode Configuration
MAX32665-MAX32668 User Guide 16.9.2 Compare Mode Configuration Configure the timer for Compare mode by doing the following: 1. Set TMRn_CN.ten = 0 to disable the timer. 2. Set TMRn_CN.tmode to 011b to select Compare mode. 3. Set TMRn_CN.pres3:TMRn_CN.pres to set the prescaler that determines the timer frequency.
Page 342: Gated Mode (110B)
MAX32665-MAX32668 User Guide 16.10 Gated Mode (110b) Gated mode is similar to continuous mode, except that TMRn_CNT only increments when the timer pin is in its active state. Figure 16-6: Gated Mode Diagram TMR_CN.TPL = 0 TIMER PIN (INPUT) TMR_CN.TPL = 1 TIMER CLOCK TMR_CN.TEN...
Page 343: Gated Mode Timer Period
MAX32665-MAX32668 User Guide 16.10.1 Gated Mode Timer Period The timer period ends when TMRn_CNT TMRn_CMP and the timer automatically performs the following actions: TMRn_CNT is reset to 0x0000 0001. The timer remains enabled and continues incrementing. 2. The timer interrupt bit TMRn_INT.irq will be set. An interrupt will be generated if enabled.
Page 344: Capture/Compare Mode (111B)
MAX32665-MAX32668 User Guide 16.11 Capture/Compare Mode (111b) In Capture/Compare mode, the timer starts counting after the first external timer input transition occurs. The transition, a rising edge or falling edge on the timer’s input signal, is set using the TMRn_CN.tpol bit.
Page 345: Timer Registers
MAX32665-MAX32668 User Guide Equation 16-11: Capture Mode Elapsed Time TMR_PWM − TMR_CNT INITIAL_CNT_VALUE Capture elapsed time in seconds = ( Hz ) CNT_CLK 16.12 Timer Registers Address offsets for the timer registers are shown in Table 16-1. Register fields marked as Reserved for Future Use should not be modified.
Page 346: Table 16-4: Timer Interrupt Registers
MAX32665-MAX32668 User Guide Table 16-4: Timer Interrupt Registers Timer Interrupt Register TMRn_INT [0x000C] Bits Name Access Reset Description 31:1 Reserved for Future Use Do not modify this field from its default value. Timer Interrupt If set, this field indicates a timer interrupt condition occurred.
Page 347 MAX32665-MAX32668 User Guide Timer Control Register TMRn_CN [0x0010] Bits Name Access Reset Description pres Timer Prescaler Select Sets the timer’s prescaler value. The prescaler divides the PCLK input to the timer and = PCLK ( Hz ) sets the timer’s count clock, f ⁄...
Page 348: Table 16-6: Timer Non-Overlapping Compare Registers
MAX32665-MAX32668 User Guide Table 16-6: Timer Non-Overlapping Compare Registers Timer Non-Overlapping Compare Register TMRn_NOLCMP [0x0014] Bits Name Access Reset Description 31:16 Reserved for Future Use Do not modify this field from its default value. 15:8 nolhcmp Non-Overlapping High Compare The 8-bit timer count value of non-overlapping time between the falling edge of PWM output ��...
Page 349: Pulse Train Engine (Pt)
MAX32665-MAX32668 User Guide 17. Pulse Train Engine (PT) Each independent pulse train engine operates either in Square Wave mode which generates a continuous 50% duty-cycle square wave, or pulse train mode which generates a continuous programmed bit pattern from 2- to 32-bits in length. Pulse train engines are used independently or may be synchronized together to generate signals in unison.
Page 350: Pulse Train Output Modes
MAX32665-MAX32668 User Guide 17.3.1 Pulse Train Output Modes Each pulse train output supports the following modes: • Pulse Train Mode • Bit Patter Length • Square Wave Mode 17.3.1.1 Pulse Train Mode When pulse train x (PTn) is configured in pulse train mode, the configuration also includes the bit length (up to 32-bits) of the custom pulse train.
Page 351: Enabling And Disabling A Pulse Train Output
MAX32665-MAX32668 User Guide If a running pulse train engine is triggered by another pulse train’s Stop Event, Automatic Restart restarts the running pulse train engine from the beginning of its pattern. If a pulse train engine is triggered by another pulse train’s Stop Event, and it is not running, Automatic Restart sets the enable bit to 1, and starts the pulse train engine.
Page 352: Pulse Train Atomic Disable
MAX32665-MAX32668 User Guide corresponding pulse train engine is already enabled and running, writing a 1 to that bit position in the PTG_SAFE_EN register has no effect. 17.5.2 Pulse Train Atomic Disable PTG_SAFE_DIS “Global Safe Disable” is a write-only register for disabling a pulse train engine without performing a RMW.
Page 353 MAX32665-MAX32668 User Guide Offset Register Description [0x0034] PTn_TRAIN PT1 Pulse Train Mode Bit Pattern [0x0038] PTn_LOOP PT1 Loop Control [0x003C] PTn_RESTART PT1 Automatic Restart [0x0040] PTn_RATE_LENGTH PT2 Configuration [0x0044] PTn_TRAIN PT2 Pulse Train Mode Bit Pattern [0x0048] PTn_LOOP PT2 Loop Control...
Page 354: Register Details
MAX32665-MAX32668 User Guide Offset Register Description [0x00F0] PTn_RATE_LENGTH PT13 Configuration [0x00F4] PTn_TRAIN PT13 Pulse Train Mode Bit Pattern [0x00F8] PTn_LOOP PT13 Loop Control [0x00FC] PTn_RESTART PT13 Automatic Restart [0x0100] PTn_RATE_LENGTH PT14 Configuration [0x0104] PTn_TRAIN PT14 Pulse Train Mode Bit Pattern...
Page 355 MAX32665-MAX32668 User Guide PT Global Enable/Disable Control PTG_ENABLE [0x0000] Bits Field Access Reset Description enable_pt9 Enable PT9 0: Disable 1: Enable Note: Disabling an active pulse train halts the output and does not generate a Stop Event. enable_pt8 Enable PT8...
Page 356: Table 17-3: Pulse Train Engine Resync Register
MAX32665-MAX32668 User Guide Table 17-3: Pulse Train Engine Resync Register PT Resync Register PTG_RESYNC [0x0004] Bits Field Access Reset Description 31:16 Reserved for Future Use Do not modify this field from its default value. pt15 Resync Control for PT15 Write 1 to reset the output of the pulse train. For pulse train mode the output is restarted to the beginning of the output pattern.
Page 357 MAX32665-MAX32668 User Guide PT Resync Register PTG_RESYNC [0x0004] Bits Field Access Reset Description pt10 Resync Control for PT10 Write 1 to reset the output of the pulse train. For pulse train mode the output is restarted to the beginning of the output pattern. For Square Wave mode the output is reset to 0.
Page 358 MAX32665-MAX32668 User Guide PT Resync Register PTG_RESYNC [0x0004] Bits Field Access Reset Description Resync Control for PT5 Write 1 to reset the output of the pulse train. For pulse train mode the output is restarted to the beginning of the output pattern. For Square Wave mode the output is reset to 0.
Page 359: Table 17-4:Pulse Train Engine Stopped Interrupt Flag Register
MAX32665-MAX32668 User Guide PT Resync Register PTG_RESYNC [0x0004] Bits Field Access Reset Description Resync Control for PT0 Write 1 to reset the output of the pulse train. For pulse train mode the output is restarted to the beginning of the output pattern. For Square Wave mode the output is reset to 0.
Page 360 MAX32665-MAX32668 User Guide PT Stopped Interrupt Flag Register PTG_INTFL [0x0008] Bits Field Access Reset Description R/W1C PT9 Stopped Status Flag This bit is set to 1 by hardware when the corresponding pulse train is in Pulse Train Mode and the loop counter reaches 0. In Square Wave mode, this field is not used.
Page 361: Table 17-5: Pulse Train Engine Interrupt Enable Register
MAX32665-MAX32668 User Guide PT Stopped Interrupt Flag Register PTG_INTFL [0x0008] Bits Field Access Reset Description R/W1C PT0 Stopped Status Flag This bit is set to 1 by hardware when the corresponding pulse train is in Pulse Train Mode and the loop counter reaches 0. In Square Wave mode, this field is not used.
Page 362 MAX32665-MAX32668 User Guide PT Interrupt Enable Register PTG_INTEN [0x000C] Bits Field Access Reset Description PT8 Interrupt Enable Write 1 to enable the interrupt for the corresponding PT when the flag is set in the PTG_INTFL register. 0: Disabled. 1: Enabled.
Page 363: Pulse Train Engine Safe Enable Register
MAX32665-MAX32668 User Guide 17.9.1 Pulse Train Engine Safe Enable Register A 32-bit value written to this register performs an immediate binary OR with the contents of PTG_ENABLE. The result is immediately stored in the PTG_ENABLE. Table 17-6: Pulse Train Engine Safe Enable Register...
Page 364: Pulse Train Engine Safe Disable Register
MAX32665-MAX32668 User Guide Pulse Train Engine Safe Enable Register PTG_SAFE_EN [0x0010] Bits Field Access Reset Description safeen_pt6 Safe Enable Control for PT6 Writing a 1 sets PTG_ENABLE.enable_pt6. 1: Enable corresponding pulse train 0: No effect safeen_pt5 Safe Enable Control for PT5 Writing a 1 sets PTG_ENABLE.enable_pt5.
Page 365 MAX32665-MAX32668 User Guide Pulse Train Engine Safe Disable Register PTG_SAFE_DIS [0x0014] Bits Field Access Reset Description safedis_pt13 Safe Disable Control for PT1 Writing a 1 clears PTG_ENABLE.enable_pt13. 1: Disable corresponding pulse train 0: No effect safedis_pt12 Safe Disable Control for PT12 Writing a 1 clears PTG_ENABLE.enable_pt12.
Page 366: Table 17-8: Pulse Train Engine Configuration Register
MAX32665-MAX32668 User Guide Pulse Train Engine Safe Disable Register PTG_SAFE_DIS [0x0014] Bits Field Access Reset Description safedis_pt2 Safe Disable Control for PT2 Writing a 1 clears PTG_ENABLE.enable_pt2. 1: Disable corresponding pulse train 0: No effect safedis_pt1 Safe Disable Control for PT1 Writing a 1 clears PTG_ENABLE.enable_pt1.
Page 367: Table 17-10: Pulse Train N Loop Configuration Register
MAX32665-MAX32668 User Guide Table 17-10: Pulse Train n Loop Configuration Register Pulse Train Loop Configuration PTn_LOOP [0x0028] Bits Field Access Reset Description 31:28 Reserved for Future Use Do not modify this field from its default value. 27:16 delay Pulse Train Delay Between Loops Sets the delay, in number of Peripheral Clock cycles, that the output pauses between loops.
Page 368 MAX32665-MAX32668 User Guide Pulse Train Automatic Restart Configuration PTn_RESTART [0x002C] Bits Field Access Reset Description on_pt_n_loop Enable Automatic Restart for this Pulse Train on a PTn Stop Event _exit 0: Disable automatic restart 1: When PTn has a Stop Event, automatically restart pulse train from the beginning of its pattern.
Page 369: Real-Time Clock (Rtc)
Disabling the RTC stops incrementing RTC_SSEC, RTC_SEC, and the internal RTC sub-second counter, but preserves their current value. The 32kHz oscillator is not affected by the RTC_CTRL.enable field. The RTC increments the RTC_TRIM.vrtc_tmr field every 32 seconds while the RTC is enabled. Figure 18-1. MAX32665―MAX32668 RTC Block Diagram (12-bit Sub-Second Counter) OPTIONAL EXT. RTC_OSCCTRL.byp...
Page 370: Instances
Instances One instance of the RTC peripheral is provided. The RTC counter and alarm registers are shown in Table 18-1. MAX32665―MAX32668 RTC Counter and Alarm Registers. Table 18-1. MAX32665―MAX32668 RTC Counter and Alarm Registers Field Length Counter Increment Minimum Maximum...
Page 371: Rtc Write Access Control
MAX32665-MAX32668 User Guide Software can use two methods to ensure valid results when reading RTC_SEC and RTC_SSEC: • Poll RTC_CTRL.ready until it reads 1 before reading the registers. • Set the RTC_CTRL.ready_int_en field to 1 to generate an RTC interrupt when the next update cycle is complete and hardware sets RTC_CTRL.ready to 1 again.
Page 372: Sub-Second Alarm
MAX32665-MAX32668 User Guide 18.4.2 Sub-Second Alarm RTC_SSECA and RTC_CTRL.ssec_alarm_en field control the sub-second alarm. Writing RTC_SSECA sets the starting value for the sub-second alarm counter. Writing the Sub-Second Alarm Enable (RTC_CTRL.ssec_alarm_en) bit to 1 enables the sub-second alarm. Once enabled, an internal alarm counter begins incrementing from the RTC_SSECA value.
Page 373: Rtc Interrupt And Wakeup Configuration
MAX32665-MAX32668 User Guide 18.4.3 RTC Interrupt and Wakeup Configuration The following are a list of conditions that, when enabled, can generate an RTC interrupt. • Time-of-Day Alarm • Sub-second Alarm • Ready field asserted high, signaling write access permitted RTC can be configured so the Time-of-day and sub-second alarms are a wakeup source for exiting the following low power modes: •...
Page 374: Rtc Calibration
MAX32665-MAX32668 User Guide compensated are used during the RTC frequency calibration procedure because they incorporate the frequency adjustments provided by the digital trim function. Table 18-3. MAX32665―MAX32668 RTC Square Wave Output Configuration Function Option Control Field P0.19: SQWOUT MCR_OUTEN.sqwout0en = 1 Output Pin* P0.27: SQWOUT...
Page 375: Figure 18-4. Internal Implementation Of Digital Trim, 4Khz
MAX32665-MAX32668 User Guide Figure 18-4. Internal Implementation of Digital Trim, 4kHz RTC_CTRL.enable = 1 RTC_TRIM = 0? (TRIM FUNCTION DISABLED) TRIM_COUNT = 1,000,000 LOOP_COUNT = 0 TRIM_COUNT = TRIM_COUNT + RTC_TRIM LOOP_COUNT = LOO P_COUNT +1 (INCREMENTS 4kHz) LOOP_COUNT =...
Page 376: Registers
MAX32665-MAX32668 User Guide Complete the following steps to perform an RTC calibration: 1. If not already, software configures and enables one of the compensated calibration frequencies as described in section Square Wave Output. 2. Measure the frequency on the square wave output pin and compute the deviation from an accurate reference clock.
Page 377: Table 18-7. Rtc Time-Of-Day Alarm Register
10:9 freq_sel Frequency Output Select Selects the RTC-derived frequency to output on the square wave output pin. See Table 18-3. MAX32665―MAX32668 RTC Square Wave Output Configuration configuration details. 0b00: 1Hz (Compensated) 0b01: 512Hz (Compensated) 0b1x: 4kHz *Note: Reset on POR only.
Page 378 MAX32665-MAX32668 User Guide RTC Control Register RTC_CTRL [0x0010] Bits Field Access Reset Description ssec_alarm_fl Sub-second Alarm Interrupt Flag This interrupt flag is set when a sub-second alarm condition occurs. This flag is a wake- up source for the processor. 0: No sub-second alarm pending.
Page 379: Table 18-10. Rtc 32Khz Oscillator Digital Trim Register
MAX32665-MAX32668 User Guide RTC Control Register RTC_CTRL [0x0010] Bits Field Access Reset Description tod_alarm_en Time-of-Day Alarm Interrupt Enable Check the RTC_CTRL.busy flag after writing to this field to determine when the RTC synchronization is complete. 0: Disable. 1: Enable. *Note: Reset on POR only.
Page 380: Watchdog Timer (Wdt)
MAX32665-MAX32668 User Guide 19. Watchdog Timer (WDT) The watchdog timer protects against corrupt or unreliable software, power faults, and other system-level problems, which may place the microcontroller into an improper operating state. When the application is executing properly, application software periodically resets the watchdog counter. If the watchdog timer interrupt is enabled and the software does not reset the counter within the interrupt time period (WDTn_CTRL.int_period), the watchdog timer generates a watchdog...
Page 381: Features
MAX32665-MAX32668 User Guide Figure 19-1: Watchdog Timer Block Diagram 19.1 Features • Sixteen programmable time periods for the watchdog interrupt 2 through 2 PCLK cycles • Sixteen programmable time periods for the watchdog reset 2 through 2 PCLK cycles •...
Page 382: Interrupt And Reset Period Timeout Configuration
MAX32665-MAX32668 User Guide As soon as possible after a reset, the application software should interrogate the WDTn_CTRL.rst_flag to determine if the reset event resulted from a watchdog timer reset. If so, application software should assume that there was a program execution error and take whatever steps necessary to guard against a software corruption issue.
Page 383: Enabling The Watchdog Timer
MAX32665-MAX32668 User Guide period of one PCLK cycle. Non-consecutive writes to WDTn_RST.wdt_rst will not cause a reset of the WDT. Attempts to modify WDTn_CTRL.wdt_en after the one PCLK cycle window will be ignored. 1. Write WDTn_RST.wdt_rst: 0x000000A5 2. Write WDTn_RST.wdt_rst: 0x0000005A 19.5...
Page 384: Register Details
MAX32665-MAX32668 User Guide 19.10 Register Details Table 19-3: Watchdog Timer Control Register Watchdog Timer Control Register WDTn_CTRL [0x0000] Bits Name Access Reset Description rst_flag WDT Reset Flag If set a watchdog system reset occurred. This field is set to 0 on a POR and is not affected by other resets.
Page 385 MAX32665-MAX32668 User Guide Watchdog Timer Control Register WDTn_CTRL [0x0000] Bits Name Access Reset Description rst_period WDT Reset Period Sets the number of PCLK cycles until a system reset occurs if the watchdog timer is not reset. This field is set to 0 on a POR and is not affected by other resets.
Page 386: Table 19-4: Watchdog Timer Reset Register
MAX32665-MAX32668 User Guide Table 19-4: Watchdog Timer Reset Register Watchdog Timer Reset Register WDTn_RST [0x0004] Bits Register Field Access Reset Description 31:8 Reserved for Future Use Do not modify this field from its reset value. wdt_rst Reset Register Writing the watchdog counter reset sequence to this register resets the watchdog counter.
Page 387: Wire Master (Owm)
AN1796: Overview of 1-Wire Technology and Its Use  www.maximintegrated.com/AN1796 • AN187: 1-Wire Search Algorithm  www.maximintegrated.com/AN187 20.1 Instances There is one instance of this peripheral. iButton is a registered trademark of Maxim Integrated Products, Inc. Maxim Integrated Page 387 of 457...
Page 388: Pins And Configuration
MAX32665-MAX32668 User Guide 20.2 Pins and Configuration The OWM pin mapping is shown in Table 20-1. Table 20-1: OWM Pin to Alternate Function Mapping Alternate Alternate Alternate Alternate Function Function 1 Function 2 Function 4 Pin Name Direction Signal Description...
Page 389: 1-Wire Protocol
MAX32665-MAX32668 User Guide If the system clock is set to 120MHz, f = 60MHz, the OWM_CLK_DIV_1US.divisor field should be set to 60 as shown in PCLK Equation 20-2. Equation 20-2: OWM Clock Divisor for �� = 120�� 60�� _��_��_1��. �� = = 60 1��...
Page 390: Figure 20-2: 1-Wire Reset Pulse
MAX32665-MAX32668 User Guide touch contact interface), which means that it is the master’s responsibility to poll the bus as needed to determine the number and types of 1-Wire devices that are connected to the bus. All communication sequences on the 1-Wire Bus are initiated by the OWM. The OWM determines when 1-Wire data transmissions begin, as well as the overall communication speed that is used.
Page 391: Figure 20-3: 1-Wire Write Time Slot
MAX32665-MAX32668 User Guide Figure 20-3: 1-Wire Write Time Slot From the slave’s perspective, the initial falling edge of the time slot triggers the start of an internal timer, and when the proper amount of time has passed, the slave samples the 1-Wire line that is driven by the master. This sampling point is in between the end of the minimum-width low pulse and the end of the time slot.
Page 392: Figure 20-5: 1-Wire Rom Id Fields
MAX32665-MAX32668 User Guide 20.3.1.2.2 Standard Speed and Overdrive Speed By default, all 1-Wire communications following reset begin at the lowest rate of speed (that is, standard speed). For 1-Wire devices that support it, it is possible for the OWM to increase the rate of communication from standard speed to overdrive speed by sending the appropriate command.
Page 393: Read Rom Command
MAX32665-MAX32668 User Guide Table 20-3: 1-Wire Slave Device ROM ID Field Field Bit Number Description Family code This 8-bit value is used to identify the type of a 1-Wire slave device. Unique ID 8-55 This 48-bit value is factory-programmed to give each 1-Wire slave device (within a given family code group) a globally unique identifier.
Page 394: Match Rom And Overdrive Match Rom Commands
MAX32665-MAX32668 User Guide 20.3.4 Match ROM and Overdrive Match ROM Commands The Match ROM command is used by the OWM to select one and only one slave 1-Wire device when the ROM ID of the device has already been determined. When transmitting this command, the master sends the command byte (that is, 55h for standard speed and 69h for overdrive speed) and then sends the entire 64-bit ROM ID for the device selected, least significant bit first.
Page 395: Resume Communication Command
MAX32665-MAX32668 User Guide After the 4-bit processing stage is complete, the return value loaded into OWM_DATA.tx_rx consists of 8 bits. The low nibble (bits 0 through 3) contains the four discrepancy flags: one for each ID bit processed. If the discrepancy bit is set to 1, it means that either two slaves with differing ID bits in that position both responded (the 2 bits read were both zero), or that no slaves responded (the 2 bits read were both 1).
Page 396: 1-Wire Operation
MAX32665-MAX32668 User Guide 20.4 1-Wire Operation Once the OWM peripheral is correctly configured, then using the OWM peripheral to communicate with the 1-Wire network involves directing the OWM to generate the proper reset, read, and write operations to communicate with the 1- Wire slave devices used in a specific application.
Page 397: Reading An 8-Bit Value From The 1-Wire Bus
MAX32665-MAX32668 User Guide To read a single bit value from the 1-Wire Bus, complete the following steps: 1. Set OWM_CFG.single_bit_mode to 1. This setting causes the OWM to transmit/receive a single bit of data at a time instead of the default 8 bits.
Page 398: Register Details
MAX32665-MAX32668 User Guide 20.7 Register Details Table 20-5: OWM Configuration Register OWM Configuration Register OWM_CFG [0x0000] Bits Field Access Reset Description 31:8 Reserved for Future Use Do not modify this field. int_pullup_enable Internal Pullup Enable Set this field to enable the internal pullup resistor.
Page 399: Table 20-6: Owm Clock Divisor Register
MAX32665-MAX32668 User Guide OWM Configuration Register OWM_CFG [0x0000] Bits Field Access Reset Description long_line_mode Long Line Mode Enable Selects alternate timings for 1-Wire communication. The recommended setting depends on the length of the wire. For lines less than 40 meters, 0 should be used.
Page 400: Table 20-8: Owm Data Register
MAX32665-MAX32668 User Guide OWM Control/Status Register OWM_CTRL_STAT [0x0008] Bits Field Access Reset Description bit_bang_oe OWM Bit-Bang Output When bit-bang mode is enabled (OWM_CFG.bit_bang_en = 1), this bit sets the state of the OWM_IO pin. Setting this bit to 1 drives the OWM_IO pin low.
Page 401: Table 20-10: Owm Interrupt Enable Register
MAX32665-MAX32668 User Guide OWM Interrupt Flag Register OWM_INTFL [0x0010] Bits Field Access Reset Description tx_data_empty R/W1C TX Empty The OWM hardware automatically sets this interrupt flag when the data transmit is complete. Write 1 to clear this flag. 0: Either no data was sent or the data in the OWM_DATA.tx_rx field has not completed transmission.
Page 402: Usb 2.0 High-Speed (Usbhs) Host Interface With Phy
MAX32665-MAX32668 User Guide 21. USB 2.0 High-Speed (USBHS) Host Interface with PHY The microcontroller includes one Universal Serial Bus (USB) Host communications peripheral with a USB physical interface (PHY). The USB Host is USB 2.0 High-Speed (USBHS) compliant, capable of transfers at 480Mbps. It supports Host mode with 12 USB buffers called endpoints.
Page 403: Usbhs Bus Signals
MAX32665-MAX32668 User Guide 21.2 USBHS Bus Signals A USB cable connects a USB Host, which controls the transfer, and a USB Device, which is controlled by the Host. The USBHS Peripheral is a USB Device. A USB cable has four conductors (three hardware signals plus ground). These signals can be duplicated more than once in a physical USB cable.
Page 404: Usbhs Reset And Clock
MAX32665-MAX32668 User Guide Endpoints support four different types of data transfers: • Control Endpoint – Always uses Endpoint 0, this endpoint is used by the USB Host to setup the USB Device for the USB Device to receive operational status from the USB Host.
Page 405: Packet Size
MAX32665-MAX32668 User Guide 21.6 Packet Size For all transfers the packet size is specified in the USBHS_INMAXP register for IN endpoints and the USBHS_OUTMAXP register for OUT endpoints. These registers specify the size of the entire transactions. 21.7 Endpoint 0 Control Transactions Endpoint 0 (EP0) is the main control endpoint and handles all USB Standard Device Requests for control transfers.
Page 406: Bulk Out Endpoints
MAX32665-MAX32668 User Guide Bulk IN Endpoint Option Description DMA Transfers If the DMA is enabled for a Bulk IN endpoint (USBHS_INCSRU.dmareqenab = 1), a DMA request is generated whenever the endpoint can accept another packet in its FIFO. The DMA request is terminated when the entire packet is loaded into the DMA or when the USBHS_INCSRL.inpktrdy bit...
Page 407: Interrupt Endpoints
MAX32665-MAX32668 User Guide Bulk OUT Endpoint Option Description Error Handling A STALL packet is used to indicate that an endpoint has an error. To shut down the Bulk OUT endpoint transfer, set USBHS_OUTCSRL.sendstall = 1. When the USBHS receives the next packet, it then sends a STALL to the Host, sets the USBHS_OUTCSRL.sentstall bit, and generates an interrupt.
Page 408: Isochronous Out Endpoints
MAX32665-MAX32668 User Guide Isochronous IN Endpoint Option Description Error Handling If an Isochronous IN endpoint receives an IN Token while the IN FIFO is empty, it creates an underrun condition. This automatically sets the USBHS_INCSRL.underrun bit and results in the USBHS sending a null packet to the USB Host.
Page 409: Usbhs Device Registers
MAX32665-MAX32668 User Guide Isochronous OUT Endpoint Option Description Error Handling – High Bandwidth High-bandwidth Isochronous OUT endpoints can transfer three 1024-byte packets in one payload. Isochronous OUT Endpoints Only To the USB bus, it appears to be a single packet of 3072 bytes. If a high-bandwidth isochronous data transmission is split into more than one packet, but if less than the expected number of packets is received by the OUT endpoint, an error condition exists.
Page 410: Usbhs Device Register Details
MAX32665-MAX32668 User Guide Offset Register Name Access Description [0x007B] USBHS_EARLYDMA USBHS Early DMA Register [0x0080] USBHS_CTUCH USBHS Hi-Speed Chirp Timeout Register [0x0082] USBHS_CTHSRTN USBHS Hi-Speed RESUME Delay Register 21.12 USBHS Device Register Details Table 21-6: USBHS Device Address Register USBHS Device Address Register...
Page 411: Table 21-8: Usbhs In Endpoint Interrupt Flags Register
MAX32665-MAX32668 User Guide USBHS Power Management USBHS_POWER [0x0001] Bits Name Access Reset Description suspendm SUSPEND Mode Enable 0: SUSPEND Mode disabled. USB will not enter SUSPEND Mode. 1: SUSPEND Mode allowed. If no activity is detected on the bus for more than 3.0ms, this USB enters low-power SUSPEND Mode.
Page 412: Table 21-9: Usbhs Out Endpoint Interrupt Flags Register
MAX32665-MAX32668 User Guide Table 21-9: USBHS OUT Endpoint Interrupt Flags Register USBHS OUT Endpoint Interrupt Flags USBHS_INTROUTFL [0x0004] Bits Name Access Reset Description 16:12 Reserved for Future Use Do not modify this field. ep11_out OUT EP11 Interrupt Status Flag 0: OUT Endpoint 11 interrupt not active.
Page 413 MAX32665-MAX32668 User Guide USBHS IN Endpoint Interrupt Enable USBHS_INTRINEN [0x0006] Bits Name Access Reset Description ep10_in IN EP10 Interrupt Enable Set to 1 to enable the interrupt IN Endpoint 10. 0: Interrupt disabled. 1: Interrupt enabled. ep9_in IN EP9 Interrupt Enable Set to 1 to enable the interrupt IN Endpoint 9.
Page 414: Table 21-11: Usbhs Out Endpoint Interrupt Enable Register
MAX32665-MAX32668 User Guide Table 21-11: USBHS OUT Endpoint Interrupt Enable Register USBHS OUT Endpoint Interrupt Enable USBHS_INTROUTEN [0x0008] Bits Name Access Reset Description 16:12 Reserved for Future Use Do not modify this field. ep11_out OUT EP11 Interrupt Enable Set to 1 to enable the interrupt for OUT Endpoint 11.
Page 415: Table 21-12: Usbhs Signaling Interrupt Status Flag Register
MAX32665-MAX32668 User Guide USBHS OUT Endpoint Interrupt Enable USBHS_INTROUTEN [0x0008] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. Table 21-12: USBHS Signaling Interrupt Status Flag Register USBHS Signaling Interrupt Status Flags USBHS_INTSIGFL [0x000A] Bits...
Page 416: Endpoint Register Access Control
MAX32665-MAX32668 User Guide Table 21-15: USBHS Register Index Select Register USBHS Register Index Select USBHS_INDEX [0x000E] Bits Name Access Reset Description Reserved for Future Use Do not modify this field. index Index Register Access Selector Each IN and OUT endpoint has memory-mapped control and status registers in addresses from 0x400B 1010 to 0x400B 1018.
Page 417: Usbhs In Endpoint Maximum Packet Size Registers
MAX32665-MAX32668 User Guide Endpoint Register USBHS_OUTMAXP USBHS_OUTCSRL USBHS_OUTCSRU USBHS_OUTCOUNT 21.12.3 USBHS IN Endpoint Maximum Packet Size Registers Endpoints 1 to 11 have a memory mapped version of this register selected using the USBHS_INDEX register. Table 21-18: USBHS IN Endpoint Maximum Packet Size Register...
Page 418: Usbhs Endpoint 0 Control Status Register
MAX32665-MAX32668 User Guide USBHS IN Endpoint Lower Control and Status USBHS_INCSRL [0x0012] Bits Name Access Reset Description clrdatatog R/W1O Clear IN Endpoint Data Toggle 1: Clear the IN Endpoint data toggle to 0. Note: Automatically cleared after set. sentstall R/W0C...
Page 419: Usbhs In Endpoint Upper Control Registers
MAX32665-MAX32668 User Guide USBHS Endpoint 0 Control Status USBHS_CSR0 [0x0012] Bits Name Access Reset Description sendstall R/W1O Send EP0 STALL Handshake Write a 1 to this bit to terminate the current Control Transaction by sending a STALL handshake. Automatically cleared after being set.
Page 420: Table 21-22: Usbhs Out Endpoint Maximum Packet Size Register
MAX32665-MAX32668 User Guide USBHS IN Endpoint Upper Control USBHS_INCSRU [0x0013] Bits Name Access Reset Description Isochronous Transfer Enable 0: Enable IN Bulk and IN Interrupt transfers 1: Enable IN Isochronous transfers mode Endpoint Direction Mode 0: Endpoint direction is OUT 1: Endpoint direction is IN Note: Ignored if endpoint is not used for both IN and OUT transactions.
Page 421: Table 21-23: Usbhs Out Endpoint Lower Control Status Register
MAX32665-MAX32668 User Guide USBHS OUT Endpoint Maximum Packet Size USBHS_OUTMAXP [0x0014] Bits Name Access Reset Description 10:0 maxpacketsize 0x000 Maximum Packet Size in a Single Transaction This is the maximum packet size, in bytes, that is transmitted for each microframe.
Page 422: Table 21-24: Usbhs Out Endpoint Upper Control Status Register
MAX32665-MAX32668 User Guide Table 21-24: USBHS OUT Endpoint Upper Control Status Register USBHS OUT Endpoint Upper Control Status Register USBHS_OUTCSRU [0x0017] Bits Name Access Reset Description autoclear Auto Clear outpktrdy 0: USBHS_OUTCSRL.outpktrdy must be cleared by firmware. 1: USBHS_OUTCSRL.outpktrdy is automatically cleared when data that is of the...
Page 423: Table 21-25: Usbhs Endpoint Out Fifo Byte Count Register
MAX32665-MAX32668 User Guide Table 21-25: USBHS Endpoint OUT FIFO Byte Count Register USBHS Endpoint OUT FIFO Byte Count USBHS_OUTCOUNT [0x0018] Bits Name Access Reset Description 15:13 Reserved for Future Use Do not modify this field. 12:0 outcount Read Number of Data Bytes in OUT FIFO Returns the number of data bytes in the packet that are read next in the OUT FIFO.
Page 424: Table 21-28: Usbhs Endpoint Count Info Register
MAX32665-MAX32668 User Guide Table 21-28: USBHS Endpoint Count Info Register USBHS Endpoint Count Info USBHS_EPINFO [0x0078] Bits Name Access Reset Description outendpoints Number of OUT Endpoints There are 11 OUT endpoints in this USBHS peripheral. 0xB: 11 OUT Endpoints. inendpoints Number of IN Endpoints Returns the number of IN endpoints in this USBHS peripheral.
Page 425: Table 21-32: Usbhs Hi-Speed Chirp Timeout Register
MAX32665-MAX32668 User Guide USBHS Early DMA USBHS_EARLYDMA [0x007B] Bits Name Access Reset Description edmaout Early DMA OUT Endpoints Enable 0: DMA Request signal for all OUT endpoints is deasserted when USBHS_INMAXP bytes have been read from an endpoint. 1: DMA Request signal for all OUT endpoints is deasserted when ( �� − 8 ) bytes have been read from an endpoint.
Page 426: Bluetooth 5 Low Energy (Le) Radio
MAX32665-MAX32668 User Guide 22. Bluetooth 5 Low Energy (LE) Radio Bluetooth 5 Low Energy (LE) radio is the latest version of the Bluetooth wireless communication standard. It is used for wireless headphones and other audio hardware, as well as for communication between various smart home and Internet of Things (IoT) devices.
Page 427: Figure 22-1: Max32665-Max32668 Bluetooth Stack Overview
Periodic advertising • High-duty cycle non-connectable advertising • Sample applications using standard profiles built on the Arm Cordio-B50 software framework Figure 22-1: MAX32665—MAX32668 Bluetooth Stack Overview BLUETOOTH STACK OVERVIEW APPLICATION HOST (Resides on one of the ARM Arm CORDIO-B50 STACK...
Page 428: Pins
The Arm Codio-B50 Stack Product Sheet and Profiles can be found at: https://www.arm.com/products/silicon-ip-wireless/wpan-software The Maxim MAX32665–MAX32668 Low Power Arm Micro Toolchain for both iOS and Windows can be found at: https://www.maximintegrated.com/en/products/microcontrollers/MAX32650.html/tb_tab2 This Toolchain includes documentation of the Arm Cordio-B50 Stack and profile examples.
Page 429: Trust Protection Unit (Tpu)
MAX32665-MAX32668 User Guide 23. Trust Protection Unit (TPU) The trust protection unit (TPU) is a collection of hardware and software mechanisms that provide advanced cryptographic security. Dedicated hardware engines greatly increase the speed of computationally intensive cryptographic algorithms. The dedicated symmetric block cipher engine provides the following features: •...
Page 430: Dedicated Cryptographic Dma Engine (Cdma)
MAX32665-MAX32668 User Guide Figure 23-1. Cryptographic Accelerator Block Diagram CRYPTO RING CIPHER FIFO IN FIFO OUT HASH DIGEST GALOIS POLY LFSR HAMMING Memories 23.1 Dedicated Cryptographic DMA Engine (CDMA) A dedicated DMA engine performs high-speed accesses between the TPU and memory on the AHB bus. This greatly improves performance during data-intensive operations such as encryption/decryption and hashing.
Page 431: Fifos
MAX32665-MAX32668 User Guide Figure 23-2. DMA Block Diagram READ FIFO WORD 0 (CRYPTO_DIN_0) WORD 1 CRYPTOGRAP HIC WORD (CRYPTO_DIN_1) DMA CONTROLLER ALIGN WORD 2 (CRYPTO_DIN_2) WORD 0 RDATA (CRYPTO_DIN_3) DMA_SRC CRYPTOGRAPHIC WDATA DMA_DEST ENGINES WRITE FI FO ADDR DMA_CNT WORD 0...
Page 432: Direct Fifo Access
MAX32665-MAX32668 User Guide The setting of the read and write FIFOs sources are detailed in each section of specific operations. For cipher, hash, or Galois operations most operations are finished when the DMA transfer is complete. If the CRYPTO_CTRL.rdsrc is configured for DMA, both the CRYPTO_CTRL.dma_done and the associated .done flag are set after the entire DMA operation is complete.
Page 433: Figure 23-3. Block Cipher Block Diagram
MAX32665-MAX32668 User Guide Figure 23-3 is a block diagram of the block cipher accelerator and its interface to the CMDA. Figure 23-3. Block Cipher Block Diagram LOAD CI PHER KEY BLOCK CIPHER ACCELERATOR CIPHER_CTRL.key CIPHER_KEY_[7:0] CIPHER_CTRL.src = 0b1x AES_KEY2 CIPHER KEY CIPHER_CTRL.src = 0b10...
Page 434: Cipher Key Storage And Initialization
MAX32665-MAX32668 User Guide For the CFB mode of operation, the mode size is equal to the block size. 128-bit CFB is supported for AES, and 64-bit CFB is supported for TDEA. 1-bit CFB and 8-bit CFB are not supported. For the CTR mode of operation, the lower 32-bits of the initial vector increment.
Page 435: Operation
MAX32665-MAX32668 User Guide The following procedure is required to load a key of 128 bits or less: 1. Clear CRYPTO_CTRL.done = 0 and CRYPTO_CTRL.dma_done = 0. 2. Set CIPHER_CTRL.src = 0b01 to copy the contents of AES_KEY_2 into CIPHER_KEY_0. 3. Poll until hardware sets CRYPTO_CTRL.dma_done = 1.
Page 436: Last Message Block Padding
MAX32665-MAX32668 User Guide Table 23-3. Hash Functions ALGORITHM DIGEST LENGTH EFFECTIVE STRENGTH BLOCK SIZE (NIST SP800-57) SHA-1 160 bits 63 bits 512 bits SHA-224 224 bits 112 bits 512 bits SHA-256 256 bits 128 bits 512 bits SHA-384 384 bits...
Page 437: Crc Engine (Galois Field Accelerator)
MAX32665-MAX32668 User Guide For SHA-1 and SHA-256, a single bit equal to 1 is appended to the end of the message. The message is then padded using software with zeros until 64 bits remain in the last 512-bit block. If less than 64 bits remain, then zeros are appended to the message until 64 bits remain in the next 512-bit block.
Page 438: Figure 23-5. Hamming Xor Calculations
MAX32665-MAX32668 User Guide Figure 23-5. Hamming XOR Calculations Byte 5 Byte 5 Byte 4 Byte 4 Byte 3 Byte 3 Byte 2 Byte 2 Byte 1 Byte 1 Byte 0 Byte 0 ECC bit0 – XOR every other bit ECC bit1 – XOR every other 2 bits...
Page 439: Modular Arithmetic Accelerator
MAX32665-MAX32668 User Guide You can save this extra ECC bit at the cost of an additional parity calculation. If the MSB of the data is set, the ECC parity bits should be XOR’d with 2n+1-1 (n 1s). This effectively swaps the MSB of the data with the MSB of the ECC for purposes of parity calculation.
Page 440: Operation
MAX32665-MAX32668 User Guide The MAA features include: • Supports up to a 2048-bit operand size • Performs up to 2048-bit modular exponentiation (ae mod m) • Performs up to 2048-bit modular multiplication (a*b mod m) • Performs up to 2048-bit modular square (b2 mod m) •...
Page 441: Table 23-5. Maa Memory Segments And Locations
MAX32665-MAX32668 User Guide The modulus (m) is always stored in memory instance 5. When an exponentiation operation is selected, the exponent (e) is always stored in memory instance 4. If another operation is selected, memory instance 4 is free to hold another parameter.
Page 442: True Random Number Generation
MAX32665-MAX32668 User Guide 23.6.2.3 Optimized Calculations The optimized calculation control bit (MAA_CTRL.ocal) allows the software to optimize the speed of an exponentiation by skipping unnecessary multiply operations when the corresponding exponent bit is a 0. The bit defaults to 0, forcing the MAA to operate in a non-optimized mode.
Page 443: Write Access
MAX32665-MAX32668 User Guide 23.8.1 Write Access MAA_CTRL register can only be written to when the MAA is idle (MAA_CTRL.stc =0). See the bit description for more details on its write access limitation. The CRYPTO_CTRL.flag_mode field determines the method used to clear the CRYPTO_CTRL.dma_done, CRYPTO_CTRL.gls_done, CRYPTO_CTRL.hsh_done, and CRYPTO_CTRL.cph_done flags.
Page 444: Register Details
MAX32665-MAX32668 User Guide Register Offset Description CIPHER_KEY_6 0x0078 Cipher Key [223:192] CIPHER_KEY_7 0x007C Cipher Key [255:224] HASH_DIGEST_0 0x0080 Hash Message Digest [31:0] HASH_DIGEST_1 0x0084 Hash Message Digest [63:32] HASH_DIGEST_2 0x0088 Hash Message Digest [95:64] HASH_DIGEST_3 0x008C Hash Message Digest [127:96]...
Page 445 MAX32665-MAX32668 User Guide Cryptographic Control Register CRYPTO_CTRL [0x0000] BITS NAME ACCESS RESET DESCRIPTION AHB Bus Error This bit is set if the DMA attempts to access non-existent or protected memory on the AHB bus. This bit can only be cleared by resetting the cryptographic accelerator block.
Page 446: Table 23-9: Cipher Control Register
MAX32665-MAX32668 User Guide Cryptographic Control Register CRYPTO_CTRL [0x0000] BITS NAME ACCESS RESET DESCRIPTION wrsrc Write FIFO Source Select This field determines the source of the write FIFO data. 0b00: None 0b01: Cipher Output 0b10: Read FIFO 0b11: Reserved wait_pol Wait Pin Polarity This feature is not implemented in this device.
Page 447: Table 23-10: Hash Control Register
MAX32665-MAX32668 User Guide Cipher Control Register CIPHER_CTRL [0x0004] BITS NAME ACCESS RESET DESCRIPTION 10:8 mode Mode Select Operating mode of block cipher or memory operation. 0b000: ECB 0b001: CBC 0b010: CFB 0b011: OFB 0b100: CTR Others: Reserved Reserved for Future Use Do not modify this field from its default value.
Page 448: Table 23-11: Crc Control Register
MAX32665-MAX32668 User Guide Hash Control Register HASH_CTRL [0x08] BITS NAME ACCESS RESET DESCRIPTION last Last Message Bit This bit is set along with the HASH MSG_SZ_3:0 register prior to hashing the last 512 or 1024-bit block of the message data. It allows automatic preprocessing of the last message padding, which includes the trailing bit 1 followed by the respective number of zero bits for the last block size and the message length represented in bytes.
Page 449: Table 23-12: Cryptographic Dma Source Register
MAX32665-MAX32668 User Guide CRC Control Register CRC_CTRL [0x000C] BITS NAME ACCESS RESET DESCRIPTION prng PRNG Enable This feature is not implemented in this device. Do not change this bit from its default value. CRC MSB select This bit selects the order of calculating CRC on data.
Page 450 MAX32665-MAX32668 User Guide MAA Control Register MAA_CTRL [0x001C] BITS NAME ACCESS RESET DESCRIPTION 0b1000 0b1001 0b1010 27:24 Result Memory Assignment These bits select the logical cryptographic RAM segment for parameter r. SETTINGS SEGMENT MAWS < 1024 MAWS ≥ 1024 0b0000...
Page 451 MAX32665-MAX32668 User Guide MAA Control Register MAA_CTRL [0x001C] BITS NAME ACCESS RESET DESCRIPTION 15:14 Modulus Memory Select These bits select the starting position of parameter m within logical segment 5. SETTING OFFSET WITHIN LOGICAL SEGMENT 0b00 None 0b01 0x0040 0b10...
Page 452: Table 23-16: Cryptographic Data Input Register
MAX32665-MAX32668 User Guide MAA Control Register MAA_CTRL [0x001C] BITS NAME ACCESS RESET DESCRIPTION Calculation Configuration These bits select the MAA calculation. 0b000: Modular exponentiation 0b001: Square operation 0b010: Multiplication 0b011: Square followed by a multiplication 0b100: Addition 0b101: Subtraction 0b110: Reserved...
Page 453: Table 23-18: Crc Polynomial Register
MAX32665-MAX32668 User Guide Table 23-18: CRC Polynomial Register CRC Polynomial Register CRC_POLY [0x0040] BITS NAME ACCESS RESET DESCRIPTION 31:0 data 0xEDB88320 CRC Polynomial This register holds the polynomial used for CRC calculations. The reset value of this register is the CRC-32 Ethernet polynomial. This register is affected by the MSB control bit.
Page 454: Table 23-23: Cipher Key Register [7:0]
MAX32665-MAX32668 User Guide Table 23-23: Cipher Key Register [7:0] Cipher Key Register0 [31:0] CIPHER_KEY_0 [0x0060] Cipher Key Register 1 [63:32] CIPHER_KEY_1 [0x0064] Cipher Key Register 2 [95:64] CIPHER_KEY_2 [0x0068] Cipher Key Register 3 [127:96] CIPHER_KEY_3 [0x006C] Cipher Key Register 4 [159:128]...
Page 455: Table 23-26: Maa Word Size Register
MAX32665-MAX32668 User Guide Table 23-26: MAA Word Size Register MAA Word Size Register MAA_MAWS [0x00D0] BITS NAME ACCESS RESET DESCRIPTION 31:12 Reserved for Future Use Do not modify this field from its default value. 11:0 msgsz MAA Word Size This register defines the number of bits for a modular operation. Valid values are from 1 to 2048.
Page 456: Table 23-27: Trng Control Register (Base Address 0X400B_5000)
Table 23-28: TRNG Data Register (Base address 0x400B_5000) MAA Word Size Register TRNG_DATA [0x0004] BITS NAME ACCESS RESET DESCRIPTION 31:0 data TRNG Data The function of this register is dependent on the rng_is and rng_i4s bits Maxim Integrated Page 456 of 457...
Page 457: Revision History
6/19 Initial Release ©2019 by Maxim Integrated Products, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. MAXIM INTEGRATED PRODUCTS, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.

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Max32666 Max32667 Max32668

Maxim Integrated MAX32665 User Manual

1 Overview

2 Resource Protection Unit (RPU)

3 Memory, Register Mapping, and Access

4 System, Power, Clocks, Reset

5 Interrupts and Exceptions

6 General-Purpose I/O and Alternate Function Pins (GPIO)

7 Flash Controller (FLC)

8 External Memory

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