Maxim Integrated MAX32665 Manuals

Manuals and User Guides for Maxim Integrated MAX32665. We have 1 Maxim Integrated MAX32665 manual available for free PDF download: User Manual

Maxim Integrated MAX32665 User Manual (457 pages)

Brand: Maxim Integrated | Category: Motherboard | Size: 6.17 MB

Table of Contents
2
1 Overview

24
- Block Diagram
  25
- Figure 1-1: MAX32665-MAX32668 Block Diagram
  25
2 Resource Protection Unit (RPU)

26
3 Memory, Register Mapping, and Access

34
- Memory, Register Mapping, and Access Overview
  34
- Figure 3-1: Code Memory Mapping
  35
- Figure 3-2: Data Memory Mapping
  36
- Standard Memory Regions
  37
  - Code Space
    37
  - SRAM Space
    37
  - Peripheral Space
    38
  - External RAM Space
    38
  - External Device Space
    39
  - System Area (Private Peripheral Bus)
    39
  - System Area (Vendor Defined)
    39
- Device Memory Instances
  39
  - Main Program Flash Memory
    39
  - Cache Memories
    39
  - External Memory Cache Controller (EMCC)
    40
  - Information Block Flash Memory
    40
  - System SRAM
    40
  - AES Key and Working Space Memory
    40
  - MAA Key and Working Space Memory
    40
  - TPU Memory
    40
- AHB Interfaces
  40
  - Core AHB Interfaces
    40
  - AHB Masters
    41
- Peripheral Register Map
  41
- Error Correction Coding (ECC) Module
  43
4 System, Power, Clocks, Reset

50
5 Interrupts and Exceptions

115
- Features
  115
- Interrupt Vector Table
  115
- Table 5-1: MAX32665-MAX32668 Interrupt Vector Table
  115
6 General-Purpose I/O and Alternate Function Pins (GPIO)

119
7 Flash Controller (FLC)

134
- Instances
  134
- Usage
  134
  - Table 7-1: MAX32665-MAX32668 Internal Flash Memory Organization
    134
  - Clock Configuration
    135
  - Flash Write Width
    135
  - Lock Protection
    135
  - Table 7-2: Valid Addresses Flash Writes
    135
  - Flash Write
    136
  - Page Erase
    136
  - Mass Erase
    137
- Flash Error Correction Coding
  137
- Flash Controller Registers
  137
- Table 7-3: Flash Controller Registers
  137
- Flash Controller Register Details
  138
- Table 7-4: Flash Controller Address Pointer Register
  138
- Table 7-5: Flash Controller Clock Divisor Register
  138
- Table 7-6: Flash Controller Control Register
  138
- Table 7-7: Flash Controller Interrupt Register
  139
- Table 7-8: Flash Controller ECC Data Register
  140
- Table 7-9: Flash Controller Data Register 0
  140
- Table 7-10: Flash Controller Data Register 1
  140
- Table 7-11: Flash Controller Data Register 2
  140
- Table 7-12: Flash Controller Data Register 3
  141
8 External Memory

142
9 Standard DMA (DMAC)

222
10 Cyclic Redundancy Check Engine (CRC)

238
- Instances
  239
- Linear Feedback Shift Register (LFSR)
  239
- Table 10-1: Common CRC Polynomials
  239
- Registers
  240
- Figure 10-1: Galois Field CRC and LFSR Architecture
  240
- Table 10-2: CRC Register Summary
  240
- Register Details
  241
- Table 10-3: CRC Control Register
  243
- Table 10-4: CRC DMA Source Register
  243
- Table 10-5: CRC DMA Destination Register
  243
- Table 10-6: CRC DMA Count Register
  243
- Table 10-7: CRC Data Input Registers
  244
- Table 10-8: CRC Data Output Registers
  244
- Table 10-9: CRC Polynomial Register
  244
- Table 10-10: CRC Value Register
  245
- Table 10-11: CRC Pseudo-Random Number Generator Register
  245
11 Analog to Digital Converter and Comparators (ADC)

246
12 Uart

260
- Instances
  260
- UART Frame
  260
- Figure 12-1: UART Frame Diagram
  260
- UART Interrupts
  261
- UART Baud Rate Clock Source
  261
- UART Baud Rate Calculation
  261
- Table 12-1: UART Interrupt Conditions
  261
- Table 12-2: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps
  262
- UART Configuration and Operation
  263
- Wakeup Time
  263
- Hardware Flow Control
  263
- Registers
  263
- Register Details
  264
- Table 12-3: UART Register Summary
  264
- Table 12-4: UART Control 0 Register
  264
- Table 12-5: UART Control 1 Register
  266
- Table 12-6: UART Status Register
  266
- Table 12-7: UART Interrupt Enable Register
  267
- Table 12-8: UART Interrupt Flags Register
  268
- Table 12-9: UART Rate Integer Register
  270
- Table 12-10: UART Baud Rate Decimal Register
  270
- Table 12-11: UART FIFO Register
  270
- Table 12-12: UART DMA Configuration Register
  270
- Table 12-13: UART Transmit FIFO Data Output Register
  271
1 I C Master/Slave Serial Communications Peripheral (I2C)

272
- Figure 13-1: I C Block Diagram
  273
  - C Master/Slave Features
    274
  - Instances
    274
  - Table 13-1: MAX32665 - MAX32668 I
    274
  - I 2 C Overview
    275
    
    I 2 C Bus Terminology
    275
    
    I 2 C Transfer Protocol Operation
    275
    
    START and STOP Conditions
    275
    
    Master Operation
    275
    
    Acknowledge and Not Acknowledge
    275
    
    Table 13-2: I 2 C Bus Terminology
    275
    
    Bit Transfer Process
    276
    
    Figure 13-2: I C Write Data Transfer
    276
  - I 2 C Configuration and Usage
    277
    
    SCL and SDA Bus Drivers
    277
    
    SCL Clock Configurations
    277
    
    SCL Clock Generation for Standard, Fast and Fast-Plus Modes
    277
    
    SCL Clock Generation for Hs-Mode
    278
    
    Figure 13-3: I C SCL Timing for Standard, Fast, and Fast-Plus Modes
    278
    
    I 2 C Addressing
    279
    
    Table 13-3: Calculated I
    279
    
    Table 13-4: I 2 C Slave Address Format
    279
    
    I 2 C Master Mode Operation
    280
    
    I 2 C Slave Mode Operation
    283
    
    I 2 C Interrupt Sources
    288
    
    TX FIFO and RX FIFO
    288
    
    TX FIFO Preloading
    289
    
    Interactive Receive Mode (IRXM)
    290
    
    Clock Stretching
    291
    
    I 2 C Bus Timeout
    291
    
    I 2 C DMA Control
    292
  - Registers
    292
  - Table 13-5: I 2 C Registers
    292
  - Register Details
    293
  - Table 13-6: I 2 C Control 0 Register
    293
  - Table 13-7: I C Status Register
    294
  - Table 13-8: I C Interrupt Flag 0 Register
    295
  - Table 13-9: I C Interrupt Enable 0 Register
    297
  - Table 13-10: I C Interrupt Flag 1 Register
    299
  - Table 13-11: I C Interrupt Enable 1 Register
    299
  - Table 13-12: I C FIFO Length Register
    299
  - Table 13-13: I C Receive Control 0 Register
    299
  - Table 13-14: I C Receive Control 1 Register
    300
  - Table 13-15: I C Transmit Control 0 Register
    301
  - Table 13-16: I C Transmit Control 1 Register
    302
  - Table 13-17: I C Data Register
    302
  - Table 13-18: I C Master Mode Control Register
    303
  - Table 13-19: I C SCL Low Control Register
    303
  - Table 13-20: I C SCL High Control Register
    303
  - Table 13-21: I C Hs-Mode Clock Control Register
    304
  - Table 13-22: I C Timeout Register
    304
  - Table 13-23: I C DMA Register
    304
  - Table 13-24: I C Slave Address Register
    305
14 Quad Serial Peripheral Interface (SPI)

306
- Figure 14-1: QSPI Block Diagram
  306
15 Htimer (HT)

324
- Overview
  324
- Alarm Functions
  324
  - Long-Interval Alarm
    324
  - Short-Interval Alarm
    324
- Register Access Control
  325
  - Register Write Protection
    325
  - Register Read Protection
    325
  - Count Register Access
    325
  - Alarm Register Access
    325
- Registers
  326
- Register Details
  326
- Table 15-1. Htimer Registers Summary
  326
- Table 15-2: Htimer Long-Interval Counter Register
  326
- Table 15-3: Htimer Short-Interval Counter Register
  326
- Table 15-4: Htimer Long-Interval Alarm Register
  326
- Table 15-5: Htimer Short-Interval Alarm Register
  326
- Table 15-6: Htimer Control Register
  327
16 Timers

329
- Features
  329
- Basic Operation
  329
- Timer Pin Functionality
  330
- One-Shot Mode (000B)
  330
  - Figure 16-1: One-Shot Mode Diagram
    330
  - One-Shot Mode Configuration
    331
  - One-Shot Mode Timer Period
    331
- Continuous Mode (001B)
  331
- Counter Mode (010B)
  334
  - Figure 16-3: Counter Mode Diagram
    334
  - Counter Mode Configuration
    335
  - Counter Mode Timer Period
    335
- PWM Mode (011B)
  336
  - PWM Mode Timer Period
    336
  - PWM Mode Configuration
    336
- Capture Mode (100B)
  338
  - Figure 16-4: Capture Mode Diagram
    338
  - Capture Mode Configuration
    339
  - Capture Mode Timer Period
    339
- Compare Mode (101B)
  339
  - Compare Mode Timer Period
    340
  - Figure 16-5: Counter Mode Diagram
    340
  - Compare Mode Configuration
    341
- Gated Mode (110B)
  342
  - Figure 16-6: Gated Mode Diagram
    342
  - Gated Mode Configuration
    343
  - Gated Mode Timer Period
    343
- Capture/Compare Mode (111B)
  344
  - Capture/Compare Timer Period
    344
  - Capture/Compare Configuration
    344
- Timer Registers
  345
- Table 16-1: Timer Register Offset, Names, Access and Descriptions
  345
- Table 16-2: Timer Count Registers
  345
- Table 16-3: Timer Compare Registers
  345
- Table 16-4: Timer Interrupt Registers
  346
- Table 16-5: Timer Control Registers
  346
- Table 16-6: Timer Non-Overlapping Compare Registers
  348
17 Pulse Train Engine (PT)

349
18 Real-Time Clock (RTC)

369
19 Watchdog Timer (WDT)

380
- Features
  381
- Usage
  381
- Figure 19-1: Watchdog Timer Block Diagram
  381
- Interrupt and Reset Period Timeout Configuration
  382
- Timed Access Protection
  382
- Table 19-1: Watchdog Timer Interrupt Period Fsys_Clk = 96Mhz and Fpclk = 48Mhz
  382
- Enabling the Watchdog Timer
  383
  - Enable Sequence
    383
- Disabling the Watchdog Timer
  383
  - Manual Disable
    383
  - Automatic Disable
    383
- Resetting the Watchdog Timer
  383
  - Reset Sequence
    383
- Detection of a Watchdog Reset Event
  383
- Registers
  383
- Table 19-2: Watchdog Timer Register Offsets, Names and Descriptions
  383
- Register Details
  384
- Table 19-3: Watchdog Timer Control Register
  384
- Table 19-4: Watchdog Timer Reset Register
  386
20 Wire Master (OWM)

387
- Instances
  387
- Pins and Configuration
  388
  - Pin Configuration
    388
  - 1-Wire I/O (OWM_IO)
    388
  - Pullup Enable (OWM_PE)
    388
  - Clock Configuration
    388
  - Table 20-1: OWM Pin to Alternate Function Mapping
    388
- 1-Wire Protocol
  389
  - Networking Layers
    389
  - Figure 20-1: 1-Wire Signal Interface
    389
  - Figure 20-2: 1-Wire Reset Pulse
    390
  - Figure 20-3: 1-Wire Write Time Slot
    391
  - Figure 20-4: 1-Wire Read Time Slot
    391
  - Figure 20-5: 1-Wire ROM ID Fields
    392
  - Table 20-2: 1-Wire ROM Commands
    392
  - Read ROM Command
    393
  - Skip ROM and Overdrive Skip ROM Commands
    393
  - Table 20-3: 1-Wire Slave Device ROM ID Field
    393
  - Match ROM and Overdrive Match ROM Commands
    394
  - Search ROM Command
    394
  - Search ROM Accelerator Operation
    394
  - Resume Communication Command
    395
- 1-Wire Operation
  396
  - Resetting the OWM
    396
- 1-Wire Data Reads
  396
  - Reading a Single Bit Value from the 1-Wire Bus
    396
  - Reading an 8-Bit Value from the 1-Wire Bus
    397
- Registers
  397
- Table 20-4: OWM Register Summary
  397
- Register Details
  398
- Table 20-5: OWM Configuration Register
  398
- Table 20-6: OWM Clock Divisor Register
  399
- Table 20-7: OWM Control/Status Register
  399
- Table 20-8: OWM Data Register
  400
- Table 20-9: OWM Interrupt Flag Register
  400
- Table 20-10: OWM Interrupt Enable Register
  401
21 USB 2.0 High-Speed (USBHS) Host Interface with PHY

402
22 Bluetooth 5 Low Energy (LE) Radio

426
- Power-Efficient Design
  426
- Bluetooth Hardware Accelerator
  426
- Arm Cordio®-B50 Software Stack
  426
- Figure 22-1: MAX32665-MAX32668 Bluetooth Stack Overview
  427
- Pins
  428
- Configuration
  428
- Documentation
  428
23 Trust Protection Unit (TPU)

429
24 Revision History

457

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Motherboard Microcontrollers Extender Computer Hardware Adapter

More Maxim Integrated Manuals

Maxim Integrated MAX32665 Manuals

Maxim Integrated MAX32665 User Manual (457 pages)

Table of Contents

1 Overview

2 Resource Protection Unit (RPU)

3 Memory, Register Mapping, and Access

4 System, Power, Clocks, Reset

5 Interrupts and Exceptions

6 General-Purpose I/O and Alternate Function Pins (GPIO)

7 Flash Controller (FLC)

8 External Memory

9 Standard DMA (DMAC)

10 Cyclic Redundancy Check Engine (CRC)

11 Analog to Digital Converter and Comparators (ADC)

12 Uart

1 I C Master/Slave Serial Communications Peripheral (I2C)

14 Quad Serial Peripheral Interface (SPI)

15 Htimer (HT)

16 Timers

17 Pulse Train Engine (PT)

18 Real-Time Clock (RTC)

19 Watchdog Timer (WDT)

20 Wire Master (OWM)

21 USB 2.0 High-Speed (USBHS) Host Interface with PHY

22 Bluetooth 5 Low Energy (LE) Radio

23 Trust Protection Unit (TPU)

24 Revision History

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