Silicon Laboratories C8051F530A User Manual page 11

7.4. Expansion I/O Connectors (J1, J2)
The two Expansion I/O connectors J1 (26 pins) and J2 (28 pins) provide access to all signal pins of the
C8051F530A devices. Pins for V
through-hole prototyping area is also provided.
All I/O signals routed to connectors J1 and J2 are also routed to through-hole connection points between J1 and J2
and the prototyping area (see Figure 3 on page 9). Each connection point is labeled indicating the signal available
at the connection point. See Table 2 for a list of pin descriptions for J1 and J2.
Pin # Description
1 P0.0_B
2 P0.1_B
3 P0.2_B
4 P0.3_B
5 P0.4_B
6 P0.5_B
7 P0.6_B
8 P0.7_B
9 P1.0_B
10 P1.1_B
11 P1.2_B
12 P1.3_B
13 P1.4_B
7.5. Target Board DEBUG Interface (HDR1, HDR2)
The DEBUG connectors (HDR1 and HDR2) provide access to the DEBUG (C2) pins of the C8051F530A parts.
They are used to connect the USB Debug Adapter to the target board for in-circuit debugging and Flash
programming. Table 3 shows the DEBUG pin definitions.
, GND, 5 V, Reset, Vbat, LIN, 3.3 V and VREFIN are also available. A small
DD
Table 2. Pin Descriptions for J1 and J2
J1
Pin # Description
14 P1.5_B
15 P1.6_B
16 P1.7_B
17 +5V
18 RST/C2CLK_B
19 VBAT
20 LIN
21 NC
22 VREGOUT_B
23 NC
24 NC
25 GND
26 GND
Table 3. DEBUG Connector Pin Descriptions
Pin #
1
2, 3, 9
4
5
6
7
8
10
C8051F530A-DK
Pin # Description
1 P0.0_A
2 P0.1_A
3 P0.2_A
4 P0.3_A
5 P0.4_A
6 P0.5_A
7 P0.6_A
8 P0.7_A
9 P1.0_A
10 P1.1_A
11 P1.2_A
12 P1.3_A
13 P1.4_A
14 P1.5_A
Description
+3 VD (+3.3 VDC)
GND (Ground)
C2D
RST (Reset)
P0.6
C2CK
Not Connected
USB Power
Rev. 0.3
J2
Pin # Description
15 P1.6_A
16 P1.7_A
17 +5V
18 RST/C2CLK_A
19 VBAT
20 LIN
21 VREFIN
22 VREGOUT_A
23 +3.3V
24 NC
25 NC
26 NC
27 GND
28 GND
11